ICX224AKF Datasheet, PDF (4/25 Pages) Sony Corporation – Diagonal 8mm (Type 1/2) Frame Readout CCD Image Sensor with Square Pixel for Color Cameras

ICX224AKF
Bias Conditions
Item
Symbol Min. Typ. Max. Unit Remarks
Supply voltage
VDD
14.55 15.0 15.45 V
Protective transistor bias
VL
∗1
Substrate clock
φSUB
∗2
Reset gate clock
φRG
∗2
∗1 _{VL setting is the VVL voltage of the vertical transfer clock waveform, or the same voltage as the VL power}
supply for the V driver should be used.
∗2 _{Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated}
within the CCD.
DC Characteristics
Item
Supply current
Symbol Min. Typ. Max. Unit Remarks
IDD
4.0
7.0 10.0 mA
Clock Voltage Conditions
Item
Symbol
Min.
Typ.
Max.
Unit
Waveform
diagram
Remarks
Readout clock voltage VVT
14.55 15.0 15.45 V
1
VVH1, VVH2
–0.05 0 0.05 V
2
VVH = (VVH1 + VVH2)/2
VVH3, VVH4
–0.2 0 0.05 V
2
VVL1, VVL2,
VVL3, VVL4
–8.0 –7.5 –7.0 V
2
VVL = (VVL3 + VVL4)/2
Vertical transfer clock
voltage
VφV
VVH3 – VVH
VVH4 – VVH
6.8 7.5 8.05 V
–0.25
0.1 V
–0.25
0.1 V
2
VφV = VVHn – VVLn (n = 1 to 4)
2
2
VVHH
1.4 V
2
High-level coupling
VVHL
1.3 V
2
High-level coupling
VVLH
1.4 V
2
Low-level coupling
VVLL
0.8 V
2
Low-level coupling
VφH
Horizontal transfer
clock voltage
VHL
VCR
4.75 5.0 5.25 V
–0.05 0 0.05 V
0.5 1.65
V
3
3
3
Cross-point voltage
Reset gate clock
voltage
VφRG
3.0 3.3 5.25 V
VRGLH – VRGLL
0.4 V
VRGL – VRGLm
0.5 V
4
4
Low-level coupling
4
Low-level coupling
Substrate clock voltage VφSUB
21.5 22.5 23.5 V
5
–4–