CXD3152AR Datasheet, PDF (36/45 Pages) Sony Corporation – Signal Processor LSI for Single-chip CCD B/W Camera

CXD3152AR
Address Symbol
37 (h) AGCWAIT
38 (h) AGCTM
39 (h) AGCHD
3A (h) DCLP
Part symbol bit
Description
Default R/W
AGCWAIT
SW
0 _{Auto gain control time constant setting}
1 Hold time (Hold_time) or feedback time (FB_time)
can be selected by the SW setting.
2 _{Hold_time = (AGCWAIT × 2 + 2) × Vt}
1D (h)
3 Vt: 1/60 (EIA), 1/50 (CCIR)
(FB_time also uses the above formula.)
4
W
Hold time/feedback time selection
5 _{0: Hold_time, 1: FB_time}
00 (h)
6
dummy
7
AGCTM
Auto gain control feedback time setting
0 _{0: Low speed, 1: High speed}
00 (h)
dummy
AGCHD
dummy
DCLP
dummy
1
2
3
W
4
5
6
7
Auto gain control hold setting
0 _{0: Normal operation, 1: Hold}
00 (h)
1
2
3
W
4
5
6
7
0
Time constant setting
1
(00: Short, 11: Long) 3 (h)
2 Insensitive range setting (0: Narrow, 1: Wide)
0
3 _{Digital clamp operation mode setting}
1
4 ^{(011: V period, 100: H period) 6 bit∗ is also used.} 1
W
5 Digital clamp function ON/OFF (= 1)
0
6^∗ Digital clamp operation mode setting
0
7
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