ICX408AK Datasheet, PDF (3/18 Pages) Sony Corporation – Diagonal 6mm (Type 1/3) CCD Image Sensor for NTSC Color Video Cameras

ICX408AK
Bias Conditions
Item
Symbol Min. Typ. Max. Unit Remarks
Supply voltage
Protective transistor bias
Substrate clock
VDD
14.55 15.0 15.45 V
VL
∗1
φSUB
∗2
∗1 _{VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL}
power supply for the V driver should be used.
∗2 _{Do not apply a DC bias to the substrate clock pin, because a DC bias is generated within the CCD.}
DC Characteristics
Item
Supply current
Symbol Min.
IDD
Typ.
4
Max. Unit Remarks
6
mA
Clock Voltage Conditions
Item
Symbol
Min.
Typ.
Max.
Unit
Waveform
diagram
Remarks
Readout clock voltage VVT
14.55 15.0 15.45 V
1
VVH1, VVH2 –0.05 0 0.05 V
2
VVH = (VVH1 + VVH2)/2
VVH3, VVH4
–0.2 0 0.05 V
2
VVL1, VVL2,
VVL3, VVL4
–8.0 –7.0 –6.5 V
2
VVL = (VVL3 + VVL4)/2
VφV
6.3 7.0 8.05 V
2
VφV = VVHn – VVLn (n = 1 to 4)
Vertical transfer clock
voltage
VVH3 – VVH
VVH4 – VVH
–0.25
–0.25
0.1 V
2
0.1 V
2
VVHH
0.3 V
2
High-level coupling
VVHL
0.3 V
2
High-level coupling
VVLH
0.3 V
2
Low-level coupling
VVLL
0.3 V
2
Low-level coupling
Horizontal transfer
VφH
clock voltage
VHL
4.75 5.0 5.25 V
3
–0.05 0 0.05 V
3
VφRG
4.5 5.0 5.5 V
4
Input through 0.1µF
capacitance
Reset gate clock
voltage
VRGLH – VRGLL
VRGL – VRGLm
0.4 V
0.5 V
4
Low-level coupling
4
Low-level coupling
VRGH
VDD VDD VDD
+0.3 +0.6 +0.9 ^V
4
Substrate clock voltage VφSUB
21.0 22.0 23.5 V
5
–3–