ICX207AKB Datasheet, PDF (3/17 Pages) Sony Corporation – Diagonal 4.5mm (Type 1/4) CCD Image Sensor for PAL Color Video Cameras

ICX207AKB
Bias Conditions
Item
Symbol Min. Typ. Max. Unit Remarks
Supply voltage
Protective transistor bias
Substrate clock
Reset gate clock
VDD 14.55 15.0 15.45 V
VL
∗1
φSUB
∗2
φRG
∗2
∗1 _{VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL}
power supply for the V driver should be used.
∗2 _{Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated}
within the CCD.
DC Characteristics
Item
Supply current
Symbol Min.
IDD
Typ.
3
Max. Unit Remarks
5
mA
Clock Voltage Conditions
Item
Symbol
Min.
Typ.
Max.
Unit
Waveform
diagram
Remarks
Readout clock voltage
Vertical transfer clock
voltage
Horizontal transfer
clock voltage
VVT
VVH1, VVH2
VVH3, VVH4
VVL1, VVL2,
VVL3, VVL4
VφV
VVH3 – VVH
VVH4 – VVH
VVHH
VVHL
VVLH
VVLL
VφH
VHL
14.55 15.0 15.45 V
–0.05 0 0.05 V
–0.2 0 0.05 V
–8.0 –7.0 –6.5 V
6.3 7.0 8.05 V
–0.25
0.1 V
–0.25
0.1 V
0.3 V
0.3 V
0.3 V
0.3 V
3.0 3.3 5.25 V
–0.05 0 0.05 V
Reset gate clock
voltage
VφRG
3.0 3.3 5.5 V
VRGLH – VRGLL
0.4 V
VRGL – VRGLm
0.5 V
Substrate clock voltage VφSUB
21.0 22.0 23.5 V
1
2
VVH = (VVH1 + VVH2)/2
2
2
VVL = (VVL3 + VVL4)/2
2
VφV = VVHn – VVLn (n = 1 to 4)
2
2
2
High-level coupling
2
High-level coupling
2
Low-level coupling
2
Low-level coupling
3
3
4
Input through 0.1µF
capacitance
4
Low-level coupling
4
Low-level coupling
5
–3–