ICX098AK Datasheet, PDF (3/21 Pages) Sony Corporation – Diagonal 4.5mm (Type 1/4) Progressive Scan CCD Image Sensor with Square Pixel for Color Cameras

ICX098AK
Bias Conditions
Item
Supply voltage
Protective transistor bias
Substrate clock
Reset gate clock
Symbol Min.
VDD
14.55
VL
φSUB
φRG
Typ.
15.0
∗1
∗2
∗2
Max. Unit
15.45 V
Remarks
∗1 _{VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL}
power supply for the V driver should be used.
∗2 _{Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated}
within the CCD.
DC Characteristics
Item
Supply current
Symbol Min.
IDD
Typ.
6.0
Max. Unit
mA
Remarks
Clock Voltage Conditions
Item
Symbol
Readout clock voltage VVT
VVH02A
VVH1, VVH2A,
VVH2B, VVH3
VVL1, VVL2A,
VVL2B, VVL3
Vertical transfer clock
voltage
Vφ1, Vφ2A,
Vφ2B, Vφ3
| VVL1 – VVL3 |
VVHH
VVHL
VVLH
VVLL
Horizontal transfer
VφH
clock voltage
VHL
Reset gate clock
voltage
VφRG
VRGLH – VRGLL
VRGL – VRGLm
Substrate clock voltage VφSUB
Min. Typ. Max. Unit
14.55 15.0 15.45 V
–0.05 0 0.05 V
Waveform
diagram
1
2
Remarks
VVH = VVH02A
–0.2 0 0.05 V
2
–5.8 –5.5 –5.2 V
2
VVL = (VVL1+VVL3)/2
5.2 5.5 5.8 V
0.1 V
0.3 V
1.0 V
0.5 V
0.5 V
3.0 3.3 5.25 V
–0.05 0 0.05 V
3.0 3.3 5.5 V
0.4 V
0.5 V
19.75 20.5 21.25 V
2
2
2
High-level coupling
2
High-level coupling
2
Low-level coupling
2
Low-level coupling
3
3
4
4
Low-level coupling
4
Low-level coupling
5
–3–