ICX081AK Datasheet, PDF (3/19 Pages) Sony Corporation – Diagonal 6mm (Type 1/3) CCD Image Sensor for PAL Color Video Cameras

ICX081AK
Bias Conditions
Item
Symbol Min. Typ. Max. Unit Remarks
Supply voltage
Protective transistor bias
Substrate clock
Reset gate clock
VDD
11.64 12.0 12.36 V
VL
∗1
φSUB
∗2
φRG
∗2
∗1 _{VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL}
power supply for the V driver should be used.
∗2 _{Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated}
within the CCD.
DC Characteristics
Item
Supply current
Symbol Min. Typ. Max. Unit Remarks
IDD
6.0
mA
Clock Voltage Conditions
Item
Symbol
Min.
Typ.
Max.
Unit
Waveform
diagram
Remarks
Readout clock voltage VVT
11.64 12.0 12.36 V
VVH1, VVH2
–0.05 0
0.05 V
VVH3, VVH4
–0.2 0 0.05 V
VVL1, VVL2,
VVL3, VVL4
–6.85 –6.5 –6.15 V
VφV
5.95 6.5 6.9 V
Vertical transfer clock
voltage
VVH3 – VVH
VVH4 – VVH
–0.25
–0.25
0.1 V
0.1 V
VVHH
0.5 V
VVHL
0.5 V
VVLH
0.5 V
VVLL
0.5 V
VφH
Horizontal transfer
clock voltage
VHL
VCR
2.7 3.3 3.6 V
–0.05 0 0.05 V
0.5 1.65
V
Reset gate clock
voltage
VφRG
2.7 3.3 3.6 V
VRGLH – VRGLL
0.4 V
VRGL – VRGLm
0.5 V
Substrate clock voltage VφSUB
17.3 18.5 19.3 V
1
2
VVH = (VVH1 + VVH2)/2
2
2
VVL = (VVL3 + VVL4)/2
2
VφV = VVHn – VVLn (n = 1 to 4)
2
2
2
High-level coupling
2
High-level coupling
2
Low-level coupling
2
Low-level coupling
3
3
3
Cross-point voltage
4
4
Low-level coupling
4
Low-level coupling
5
–3–