CXA1854AR Datasheet, PDF (3/45 Pages) Sony Corporation – Decoder/Driver/Timing Generator for Color LCD Panels

CXA1854AR
Pin Description
(H: Pull up, M: Intermediate setting, L: Pull down)
Pin
No.
Symbol I/O
Description
Input pin for
open status
1 SYNC IN I Sync input
2 Y IN
I Y signal input
3 AGCADJ I AGC level adjustment
4 AGCTC
O AGC time constant
5 PICT
I Y signal frequency characteristics adjustment
6 GND1
Analog 5V GND
7 MODE1
I Switches between NTSC (H), DPAL^∗ (M) and SPAL^∗ (L)
M
8 MODE2
I Switches between composite (H), Y/color difference (M) and YC input (L)
M
9 EXT-R
I External digital input R (input conditions noted separately)
10 EXT-G
I External digital input G (input conditions noted separately)
11 EXT-B
I External digital input B (input conditions noted separately)
12 RPD
O Phase comparator output
13 VSS
Digital GND
14 CKI
I Oscillation cell input
15 CKO
O Oscillation cell output
16 TEST2
I Test
L
17 TEST1
I Test
L
18 TEST0
I Test
L
19 SLCK
I Switches between LCX005BK (H) and LCX009AK (L)
L
20 TEST3
O Leave this pin open.
21 VST1
O V start pulse 1 output
22 VCK2
O V clock pulse 2 output
23 VCK1
O V clock pulse 1 output
24 EN
O EN pulse output
25 CLR
O CLR pulse output
26 TEST4
O Leave this pin open.
27 HST1
O H start pulse 1 output
28 HCK2
O H clock pulse 2 output
29 HCK1
O H clock pulse 1 output
30 HD
O HD pulse output
31 VD
O VD pulse output
32 TEST5
I Leave this pin open.
L
∗ _{DPAL supports demodulation methods which use an external delay line during demodulation; SPAL supports}
methods which internally process chroma demodulation.
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