CXA2094Q Datasheet, PDF (28/31 Pages) Sony Corporation – US Audio Multiplexing Decoder

CXA2094Q
• I²C data Write (Write from I²C controller to the IC)
SDA
MSB
L during Write
HIZ
MSB
LSB
HIZ
SCL
S
MSB
1
2
3
4
5
6
7
8
9
1
8
9
Address
LSB
HIZ
ACK
Sub Address
ACK
HIZ
1
DATA (n)
8
9
1
8
9
ACK
HIZ
DATA (n + 1)
ACK
HIZ
DATA (n + 2)
8
9
DATA
ACK
1
DATA
8
9
P
ACK
∗ _{Data can be transferred in 8-bit units to be}
set as required.
Sub address is incremented automatically.
• I²C data Read (Read from the IC to I²C controller)
SDA
H during Read
HIZ
SCL
1
S
6
7
8
9
1
Address
ACK
7
8
DATA
9
P
ACK
• Read timing
MSB
LSB
IC output SDA
SCL
9
1
2
3
4
5
6
7
8
9
Read timing
ACK
DATA
ACK
∗ _{Data Read is performed during SCL rise.}
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