CXP921064A Datasheet, PDF (26/33 Pages) Sony Corporation – CMOS 16-bit Single Chip Microcomputer

CXP921064A
(7) Serial transfer (CH3) [Special mode]
Item
SO cycle time^∗
Symbol Pins
tLCY
SO3
SI3
SI input setup time
tLSU
SI3
(Topr = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V reference)
Conditions
Min. Typ. Max. Unit
104
fEX = 20MHZ
2
SI input hold time
tLHD SI3
2
µs
Input start bit high level
width
tLSBH SI3
1
Communication slave mode
SI → SO
delay time
tLIO
SO3
1
∗ _{When lower 2 bits (SCK1, SCK0) of serial mode register (SIOM3: 0001A4h) is specified to "00".}
Note) The load condition for the SO output delay time is 100pF.
SO3
SI3
SI3
SO3
tLCY
tLCY
Start bit
Output data bit
0.5VDD
tLCY/2
tLSU tLHD
Input data
bit
0.8VDD
0.2VDD
Fig.9. Serial transfer CH3 timing (Special mode)
tLSBH
tLSU
tLCY/2
tLHD
tLCY
tLCY
tLIO
Input data bit
0.8VDD
0.2VDD
tLSU
tLHD
tLCY
0.5VDD
Output data bit
Fig.10. Serial transfer CH3 timing (Special mode)
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