CXD2027Q Datasheet, PDF (24/32 Pages) Sony Corporation – DBS Audio Signal Processor

I²C bus control table
SASL
Slave address
LH
D4 D6
CXD2027Q/R
R/W
Sub-
address
MSB
bit7
bit6
bit5
Data
bit4
bit3
00'H
A1S1
A1S2
A1S3
A2S1
01'H
DOS1
02'H BUSMT1 BUSMT2 AMUTE SIG MTOF0
03'H OTSTP1 OTSTP2 OTSTP3 OTSTP4 NF1
WR
04'H DASLC C1SL
LRSL
IIS
BLFS
05'H
C2
06'H (TSB0) (TSB1) XEOFF XINH
PI1
07'H RGOF1 RGOF2 RGOF3 RGOF4 OTSL
00'H
CC1
CC2
CC3
CC4
CC5
RD 01'H
CC9
CC10 CC11 CC12 CC13
02'H
(L)
(L)
(L)
(L)
RG81
Blanks : Data not related to internal logic.
()
: Data for testing. Fix to the default value.
(L)
: Low is output.
MSB, LSB : Data is transmitted with MSB first.
bit2
A2S2
DOS2
MTOF1
NF2
FPCC
C10
PI2
MFRAM
CC6
CC14
RG82
bit1
A2S3
DOS3
MTOF2
TH1
FPCB
XPRT
NR
(TEST2)
CC7
CC15
RG83
LSB
bit0
MTOF3
TH2
(TEST1)
DOMU
(TEST3)
CC8
CC16
RG84
Default data (default value of internal register after master reset)
W
Sub-
address
MSB
bit7
bit6
bit5
Data
bit4
bit3
bit2
LSB
bit1
bit0
00'H
0
1
0
—
0
1
0
—
01'H
—
—
—
—
0
1
0
—
02'H
0
0
1
0
1
1
1
1
03'H
0
0
0
0
0
1
0
1
WR
04'H
0
0
0
0
1
0
1
(0)
05'H
—
—
—
—
1
1
0
0
06'H
(0)
(0)
1
0
0
0
0
—
07'H
1
1
1
1
0
0
(0)
(0)
( ) : Always fix to the default value.
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