CXA3355AER Datasheet, PDF (24/29 Pages) Sony Corporation – GPS Down Converter IC

CXA3355AER
7. PLL/VCO
The PLL is comprised by a VCO, frequency divider and phase/frequency comparator as shown in the figure
below, and incorporates an inductor, varactor and all other necessary components. The loop filter is
externally connected. Use components that satisfy the required characteristics.
Serial data setting is unnecessary when this IC is used with the typical TCXO and IF combinations set by
the initial settings shown in page 18.
When making serial data settings, set counter frequency division values that satisfy the following equations.
Š fVCO = (M × N + A) × (fTCXO × 2)/R
Š (fTCXO × 2)/R > 800kHz
Š N ≥ 3, R ≥ 3
fVCO: VCO oscillation frequency, fTCXO: TCXO frequency
MC data = N, SC data = A, RC data = R, DMPS data = M = 24 (fixed)
To the RF phase shifter
VCO
DMPS
1/M, 1/(M + 1)
∗ _{M = 24}
MC
Frequency division ratio (M × N) + A
1/N
Loop filter
VCC1
SC
PFD
CP
17
1/A
RC
×2
1/R
TCXO (10MHz to 26MHz)
14
8. ENABLE (Pin 43)
Active mode and power save mode can be switched according to the level.
Š High (V_IH: 1.2V min.): Active mode
Š Low (V_IL: 0.2V max.): Power save mode
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