CXD2724AQ-1 Datasheet, PDF (19/65 Pages) Sony Corporation – Single-Chip Dolby Pro Logic Surround Decoder

CXD2724AQ-1
(4) Details of Communication Methods
The definitions of signal timing required for control from the microcomputer are given below.
(4)-1. Initializing the Microcomputer Interface
The microcomputer interface must be initialized after resetting the IC.
After resetting the IC (t1 ≥ 1/fs), input 16 SCK rising edges. After that, REDY goes Low within 4t + 50ns (t2),
and initialization is completed when REDY goes High again. Set RVDT Low while inputting SCK.
Note that the REDY Low time (t3) is a maximum of 1/fs. See the following page for the SCK restrictions. The
same restrictions apply as during data transfer.
When REDY goes Low due to initialization:
• The SCK for the first transfer can rise.
• The XLAT for the first transfer can fall.
However, the XLAT for the first transfer must rise after REDY goes High.
RVDT
XRST
SCK
REDY
16 rising edges
t1
t2
t3
Microcomputer interface can be used
Fig. 5-2. Initialize Specifications
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