CXP87940 Datasheet, PDF (18/28 Pages) Sony Corporation – CMOS 8-bit Single Chip Microcomputer

CXP87940/87948
(2) Serial transfer (CH0)
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol Pin
Condition
Min.
Max. Unit
CS0 ↓ → SCK0
delay time
CS0 ↑ → SCK0
floating delay time
CS0 ↓ → SO0
delay time
tDCSK SCK0
tDCSKF SCK0
Chip select transfer mode
(SCK = output mode)
Chip select transfer mode
(SCK = output mode)
tDCSO SO0 _{Chip select transfer mode}
tsys + 200 ns
tsys + 200 ns
tsys + 200 ns
CS0 ↓ → SO0
floating delay time
tDCSOF SO0 _{Chip select transfer mode}
tsys + 200 ns
CS0
High level width
SCK0
cycle time
SCK0
High and Low level widths
SI0 input setup time
(for SCK0 ↑)
SI0 input hold time
(for SCK0 ↑)
SCK0 ↓ → SO0 delay time
tWHCS CS0
tKCY SCK0
tKH
tKL
SCK0
tSIK
SI0
tKSI
SI0
tKSO SO0
Chip select transfer mode
Input mode
Output mode
Input mode
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
tsys + 200
ns
2tsys + 200
ns
16000/fc
ns
tsys + 100
ns
8000/fc – 100
ns
–tsys + 100
ns
200
ns
2tsys + 100
ns
100
ns
2tsys + 200 ns
100
ns
Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 00FEH) upper
2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”)
Note 2) The load of SCK0 output mode and SO0 output delay time is 50pF + 1TTL.
– 18 –