CXK79M72C165GB Datasheet, PDF (18/29 Pages) Sony Corporation – 18Mb 1x1Dp LVCMOS High Speed Synchronous SRAMs (256Kb x 72 or 512Kb x 36)

SONY® ΣRAM
CXK79M72C165GB / CXK79M36C165GB
Preliminary
•Test Mode Description
These devices provide a JTAG Test Access Port (TAP) and Boundary Scan interface using a limited set of IEEE std. 1149.1
functions. This test mode is intended to provide a mechanism for testing the interconnect between master (processor, con-
troller, etc.), SRAMs, other components, and the printed circuit board.
In conformance with a subset of IEEE std. 1149.1, these devices contain a TAP Controller and four TAP Registers. The TAP
Registers consist of one Instruction Register and three Data Registers (ID, Bypass, and Boundary Scan Registers).
The TAP consists of the following four signals:
TCK:
TMS:
TDI:
TDO:
Test Clock
Test Mode Select
Test Data In
Test Data Out
Induces (clocks) TAP Controller state transitions.
Inputs commands to the TAP Controller. Sampled on the rising edge of TCK.
Inputs data serially to the TAP Registers. Sampled on the rising edge of TCK.
Outputs data serially from the TAP Registers. Driven from the falling edge of TCK.
Disabling the TAP
When JTAG is not used, TCK should be tied “low” to prevent clocking the SRAM. TMS and TDI should either be tied “high”
through a pull-up resistor or left unconnected. TDO should be left unconnected.
Note: Operation of the TAP does not disrupt normal SRAM operation except when the EXTEST-A or SAMPLE-Z instruc-
tion is selected. Consequently, TCK, TMS, and TDI can be controlled any number of ways without adversely affecting the
functionality of the device.
JTAG DC Recommended Operating Conditions
(V_DD = 1.7V to 1.95V, T_A = 0 to 85°C)
Parameter
JTAG Input High Voltage (TCK, TMS, TDI)
JTAG Input Low Voltage (TCK, TMS, TDI)
JTAG Output High Voltage (TDO)
JTAG Output Low Voltage (TDO)
JTAG Output High Voltage (TDO)
JTAG Output Low Voltage (TDO)
JTAG Input Leakage Current
JTAG Output Leakage Current
Symbol Test Conditions
V_TIH
V_TIL
V_TOH
V_TOL
V_TOH
V_TOL
I_TLI
I_TLO
---
---
I_TOH = -100uA
I_TOL = 100uA
I_TOH = -8mA
I_TOL = 8mA
V_TIN = V_SS to V_DD
V_TOUT = V_SS to V_DD
Min
V_DD/2 + 0.3
-0.3
V_DD - 0.1
---
V_DD - 0.4
---
-20
-10
Max
V_DD + 0.3
V_DD/2 - 0.3
---
0.1
---
0.4
10
10
Units
V
V
V
V
V
V
uA
uA
JTAG AC Test Conditions
Parameter
JTAG Input High Level
JTAG Input Low Level
JTAG Input Rise & Fall Time
JTAG Input Reference Level
JTAG Output Reference Level
JTAG Output Load Condition
Symbol
V_TIH
V_TIL
Conditions
1.8
0.0
1.0
0.9
0.9
(V_DD = 1.7V to 1.95V, T_A = 0 to 85°C)
Units
V
V
V/ns
V
V
Notes
See Fig. 1 (page 14)
18Mb 1x1Dp, LVCMOS, rev 1.3
18 / 29
November 18, 2003