CXD1968AR Datasheet, PDF (17/97 Pages) Sony Corporation – DVB-T Demodulator

CXD1968AR
3. Description of Operation
This section describes the operation of the CXD1968AR DVB-T COFDM demodulator IC and how to make use
of these features when operating the device. It does not give a detailed description of the enhanced modes of
operation, users should refer to the separate engineering application notes for additional information about
these configurations and uses.
The following descriptions apply to the CXD1968AR used with a tuner providing a High IF signal at a nominal
frequency of 36.1667MHz. Contact Sony for configuration recommendations when operating with Low IF
(4.5MHz) or Zero IF at the e-mail support address [e-mail]
EAN-0065 and EAN-0066 are intended to assist users familiar with its predecessor the CXD1976R, and intend
to make the transition to the CXD1968AR.
Engineering Application Notes are available for download to registered users from the Sony Technical Library
http://www.sonybiz.net/semiconductor.
‹ Processor Interface
The CXD1968AR must be configured by a host controller, which is required for initialization and to monitor its
performance by writing and reading the CXD1968AR internal registers. The CXD1968AR controller interface
is a serial interface which corresponds to the I²C standard. The I²C interface supports access at bit rates up to
400kbit/s.
The I²C uses an 8-bit address:
Š The first 6 significant bits relate to the device type and are fixed at 110110.
Š A single external address pin A0 is provided so that 2 different I²C slave address locations can be used.
This permits multiple front-end configurations, for instance PVR application.
Š The least significant bit is set to “1” for a write and “0” for a read.
Address pin
A0
0
1
CXD1968AR I²C address
Binary
Hexadecimal
1101 100 R/W
D8h + R/W
1101 101 R/W
DAh + R/W
Examples used in this document assume an I²C address of 0xD8.
Reference to 0xD8 indicates a write instruction and to 0xD9 indicates a read instruction.
Multibyte Reads
Some registers contain fields more than 8 bits which are each accommodated across two or three
registers. It is therefore possible for the field value to change in the time between two reads from the
register pair. When a “1” is written to the freeze bit in the PIR_CTL register (whether it was previously “0”
or not), the field values are latched and the multibyte value can be read without fear of reading a corrupt
value. With the freeze bit set to “0” the data within the fields changes dynamically.
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