CXD3057R Datasheet, PDF (16/27 Pages) Sony Corporation – CD Digital Signal Processor with Built - in RF Amplifier and Digital Servo, Digital High - Bass Boost

CXD3057R
(3) SCLK pin
XLAT
tDLS
tSPW
SCLK
...
1/fSCLK
Serial Read Out Data
(SENS)
MSB
...
LSB
(VDD = XVDD = 2.5 ± 0.2V, IOVDD0 to 2 = AVDD0 to 5 = 3.3 ± 0.3V, VSS = XVSS = IOVSS = AVSS = 0V,
Topr = –40 to +85°C)
Item
SCLK frequency
SCLK pulse width
Delay time
Symbol Min.
Typ.
Max. Unit
fSCLK
16 MHz
tSPW
31.3
ns
tDLS
15
µs
(4) COUT, MIRR and DFCT pins
Operating frequency
(VDD = XVDD = 2.5 ± 0.2V, IOVDD0 to 2 = AVDD0 to 5 = 3.3 ± 0.3V, VSS = XVSS = IOVSS = AVSS = 0V,
Topr = –40 to +85°C)
Item
COUT maximum operation frequency
MIRR maximum operation frequency
DFCT maximum operation frequency
Symbol
fCOUT
fMIRR
fDFCTH
∗1 _{When using a high-speed traverse TZC}
∗2
Min.
Typ.
40
40
5
B
Max.
Unit Conditions
kHz
∗1
kHz
∗2
kHz
∗3
A
When the RF signal continuously satisfies the following conditions during the traverse.
• A = 0.11VDD to 0.23VDD
•
B
A+B
≤ 25%
∗3 _{During complete RF signal omission.}
When settings related to DFCT signal generation are Typ.
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