English
Language : 

CXA1741Q Datasheet, PDF (16/21 Pages) Sony Corporation – IF Amplifier for Analog Cellular Communications
CXA1741Q
Notes on Operation
1. This IC must be handled with care because it is extremely susceptible to electrostatic surges. Particularly,
IFIN (Pin 22) is easily affected by electrostatic surges.
2. When the 0.1µF capacitor connected to Pin 14 has a capacitance of 0.047µF or less, the IC malfunctions.
Be sure that the employed capacitor has an excellent temperature characteristics.
3. When the capacitance value of the 0.1µF capacitor connected to Pin 38 is decreased, the IC
characteristics begin to slightly deteriorate. Further, a capacitance value increase would not improve the
IC characteristics accordingly.
4. When the capacitance value of the 0.1µF capacitor connected to Pin 40 is decreased, the IC
characteristics slightly deteriorate.
5. Vcc1 (Pin 33) supplies the power to the reference bias voltage generator circuit which is necessary for IC
operations. If the same VCC power supply is not provided for Vcc voltages to be applied to Pins 11, 19, 24,
and 33, ensure that the Pin 33 Vcc rises first.
6. Be sure that nothing is connected to Pins 13, 15, 30, 31, 32, and 35.
7. Resistance between Pins 36 and 37
The signal of 45 MHz, –50 dBm is input from Pin 22 (IFIN) and the level of Pin 3 (BPFOUT) is read. After
that when this frequency is varied to +8 kHz and –8 kHz respectively, resistance value between Pins 36
and 37 is varied to be the same attenuation level.
8. Inductance between Pins 26 and 27
Adjustment must be made so that a 45 MHz parallel resonance circuit is formed by the inductor between
Pins 26 and 27 and the IC stray capacitor. This adjustment assures that an increased mixer conversion
gain is provided at a low input signal level.
Once the optimum value is obtained upon PCB conductive pattern determination, readjustment is
unnecessary after sample changes.
9. Pin 19 resonance circuit
This circuit must be adjusted for the crystal oscillation frequency. Once the optimum value is obtained upon
PCB conductive pattern determination, readjustment is unnecessary after sample changes.
—16—