ICX432DQF Datasheet, PDF (15/30 Pages) Sony Corporation – Diagonal 6.67mm (Type 1/2.7) Frame Readout CCD Image Sensor with a Square Pixel for Color Cameras

Drive Circuit
3.3V
–7.5V 15V
0.1
XSUB
XV3
XSG3B
XSG3A
XV5
XSG5B
XSG5A
XV4
XV2
3.3V
0.1
XV1
XSG1
XV6
1
20
2
19
3
18
4
17
5
16
CXD3400N
6
15
7
14
8
13
9
12
10
11
1/35V
0.1
0.1
1
20
2
19
3
18 _0.1
4
17
5
16
CXD3400N
6
15 _0.1
7
14
8
13
9
12
10
11
100k
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ICX432DQF
(BOTTOM VIEW)
VSUB Cont.
VR1 (3.9kΩ )
18 17 16 15 14 13 12 11 10
ICX432DQF
2SC4250
CCD OUT
4.7k
3.3/20V
0.01
Hφ2
Hφ1
φRG
Substrate bias
control signal
VSUB Cont.
Mechanical
shutter mode
Substrate bias ^{tf ≈ 17ms}
φSUB pin voltage
tr ≈ 2ms
GND
Internally
generated
value VSUB
0.1
0.1
1M 3.3/16V
0.1
Notes) Substrate bias control
1. The saturation signal level decreases when exposure is performed using the mechanical shutter,
so control the substrate bias.
2. A saturation signal level equivalent to that for continuous exposure can be assured by connecting
a VR1 grounding registor to the CCD CSUB pin.
Drive timing precautions
1. Blooming occurs in modes (high frame rate readout, etc.) that do not use the mechanical shutter,
so do not ground the connected VR1 resistor.
2. tf is slow, so the internally generated voltage VSUB may not drop to a sufficiently low level if the
substrate bias control signal is not set to high level 30ms before entering the exposure period
and the VR1 resistor connected to the CSUB pin is not grounded.
3. The blooming signal generated during exposure in mechanical shutter mode is swept by providing
two fields or more of idle transfer through vertical register high-speed sweep transfer from the
time the mechanical shutter closes until sensor readout is performed. However, note that the VL
potential and the φSUB pin DC voltage sag at this time.
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