CXP827P16 Datasheet, PDF (15/21 Pages) Sony Corporation – CMOS 8-bit Single Chip Microcomputer

CXP827P16
(2) Serial transfer
(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Item
Symbol Pin
Condition
Min.
Max. Unit
CS0 ↓→ SCK0 (CS1 ↓→ SCK1)
delay time
CS0 ↑→ SCK0 (CS1 ↑→ SCK1)
float delay time
CS0 ↓→ SO0 (CS1 ↓→ SO1)
delay time
CS0 ↑→ SO0 (CS1 ↑→ SO1)
float delay time
tDCSK ^{SCK0 Chip select transfer mode}
(SCK1) ^{(SCK0 (SCK1) = output mode)}
tDCSKF ^{SCK0 Chip select transfer mode}
(SCK1) ^{(SCK0 (SCK1) = output mode)}
tDCSO ^SO0 _{Chip select transfer mode}
(SO1)
tDCSOF ^SO0 _{Chip select transfer mode}
(SO1)
tsys + 200 ns
tsys + 200 ns
tsys + 200 ns
tsys + 200 ns
CS0 (CS1) high level width
tWHCS
SCK0 (SCK1) cycle time
tKCY
SCK0 (SCK1)
tKH
High and Low level widths
tKL
SI0 (SI1) input setup time
(for SCK0 ↑ (SCK1 ↑) )
tSIK
SI0 (SI1) input hold time
(for SCK0 ↑ (SCK1 ↑) )
tKSI
SCK0 ↓→ SO0 (SCK1 ↓→ SO1)
delay time
tKSO
CS0 _{Chip select transfer mode}
(CS1)
SCK0 ^{Input mode}
(SCK1) _{Output mode}
SCK0 ^{Input mode}
(SCK1) _{Output mode}
SI0
(SI1)
SCK0 (SCK1) input mode
SCK0 (SCK1) output mode
SI0
(SI1)
SCK0 (SCK1) input mode
SCK0 (SCK1) output mode
SO0 ^{SCK0 (SCK1) input mode}
(SO1) _{SCK0 (SCK1) output mode}
tsys + 200
ns
2tsys + 200
ns
16000/fc
ns
tsys + 100
ns
8000/fc–5
ns
0
ns
100
ns
200
ns
tsys + 200
ns
100 tsys + 200 ^ns
100 ^ns
Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selected) of the
control clock registor (address: 00FEH).
tsys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")
Note 2) The load condition for the SCK0 (SCK1) output mode, SO0 (SO1) output delay time is 50pF+1TTL.
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