CXD2403AR Datasheet, PDF (14/25 Pages) Sony Corporation – Timing Generator for Color Liquid Crystal Panel

CXD2403AR
Variable Range from the Center of Sync Signal to Hst Rise Timing
HP4 HP3 HP2 HP1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
108CLK (10.7µs)
106CLK
104CLK
102CLK
100CLK
98CLK
96CLK
94CLK (9.4µs)
92CLK
90CLK
88CLK
86CLK
84CLK
82CLK
80CLK
78CLK (7.8µs)
HP1 to HP4 pins can be used to vary the
interval from the center of sync signal to HST
rise as shown in the left table.
Internal preset:
NTSC (typ.):
PAL (typ.):
1001 (90CLK)
1001 (90CLK)
1000 (92CLK)
Liquid Crystal Panel Driving Pulse Generation
HST, HCK1, HCK2, VST, VCK1, and VCK2 (EN, CLR
in LCX005 mode only) are generated for the liquid
crystal panel driver.
External Sample-and-Hold Pulse Generation
Timing pulses of external sample-and-hold circuit
SH1, SH2, and SH3 are generated.
AC Driving Pulse Generation
FRP is output for liquid crystal AC driving. Field
inverts when F/H input pin is High and line inverts when
Low. Polarity is not specified for each field. The point is
changed from VCK1 and VCK2 pulse change points
after 1 clock.
HD-Clamp Pulse Generation
HD pulse is output during horizontal BLK in order to
drive the backlight (fluorescent tube). Even during no
signal, raster screen with no screen noise can be
created synchronizing to the free running frequency.
XCLP is output for BF timing clamp pulse.
SYNC
BLK
HD
XCLP
1.5µs
4.7µs
10.9µs
2.7µs
6.1µs
6.5µs
2µs
1.4µs
1.3µs
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