CXD3005R Datasheet, PDF (130/136 Pages) Sony Corporation – CD Digital Signal Processor with Built-in Digital Servo and DAC

CXD3005R
FCS Servo Gain Normal; Fs = 88.2kHz, during quasi double accuracy (Ex.: $3EAXX0)
FCS
Hold Reg 2
DFCT
FCS
In Reg
2^–1
K06
AGFON
Sin ROM
K06
M03
Z^–1
∗
81H
2^–7
K08
M04
Z^–1
∗
7FH K0A
2^–7
K09
2^–7
K0B
K0F
M05
FCS
Hold Reg 1
Z^–1
∗
K0C 80H
2^–7
K0D
2^–7
K0E
FCS
AUTO Gain
M06
M07
K11
K13
Z^–1
K10
2⁷
FCS PWM
FCS SRCH
∗ _{81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy.}
Note) Set the MSB bit of the K0B and K0D coefficients during normal operation, and of the K08, K09
and K0E coefficients during quasi double accuracy to 0.
FCS Servo Gain Down; Fs = 88.2kHz, during quasi double accuracy (Ex.: $3E5XX0)
FCS
Hold Reg 2
DFCT
2^–1
FCS
K06
In Reg
M03
Z^–1
∗
81H
2^–7
K24
M04
Z^–1
∗
7FH K26
2^–7
K25
2^–7
K27
K2B
M05
FCS
Hold Reg 1
Z^–1
∗
K28 80H
2^–7
K29
2^–7
K2A
FCS
AUTO Gain
M06
M07
K2D
K13
Z^–1
K2C
2⁷
FCS PWM
FCS SRCH
∗ _{81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy.}
Note) Set the MSB bit of the K27 and K29 coefficients during normal operation, and of the K24, K25
and K2A coefficients during quasi double accuracy to 0.
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