CXK77V3211Q Datasheet, PDF (12/18 Pages) Sony Corporation – 32768-word by 32-bit High Speed Synchronous Static RAM

CXK77V3211Q
Write Timing (Pipeline)
CLK
ADSP
ADSC
ADDR.
BW1 to BW4
CE
(∗2)
ADV
OE
D
Q
tKC
tKH tKL
tS tH
tS tH
tS tH
A1
A2
BYTE WRITE signal are ignored for first
cycle when ADSP intiates burst
ADSC extends burst
tS tH
A3
tS tH
tS tH
(∗3)
High-Z
tS tH
D (A1)
tOHZ
tS tH
(∗4)
ADV suspends burst
D (A2)
D
(A2 + 1)
(∗1)
D
(A2 + 1)
D
(A2 + 2)
D
(A2 + 3)
D (A3)
D
(A3 + 1)
D
(A3 + 2)
Burst READ Single WRITE
Burst WRITE
Extended Burst WRITE
DON'T CARE
UNDEFINED
∗1 _{Q (A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst address}
following A2.
∗2 _{CE2 and CE2 have timing identical to CE. On this diagram, when CE is LOW, CE2 is LOW and CE2 is}
HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW.
∗3 _{OE must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents}
input/output data contention for the time period prior to the byte write enable inputs being sampled.
∗4 _{ADV must be HIGH to permit a WRITE to the loaded address.}
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