CXL5515M Datasheet, PDF (1/9 Pages) Sony Corporation – CMOS-CCD 1H Delay Line for PAL

CXL5515M/P
CMOS-CCD 1H Delay Line for PAL
Description
The CXL5515M/P are CMOS-CCD delay line ICs
designed for processing video signals. This ICs
provide a 1H delay time for PAL chroma signals
including the external lowpass filter.
Features
• Single 5V power supply
• Low power consumption
• Built-in peripheral circuit
• Built-in tripling PLL circuit
• Center bias mode
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VDD
+6
V
• Operating temperature Topr –10 to +60 °C
• Storage temperature Tstg –55 to +150 °C
• Allowable power dissipation
PD
CXL5515M 350 mW
CXL5515P 480 mW
Recommended Operating Range (Ta = 25˚C)
VDD 5V ± 5%
Recommended Clock Conditions (Ta = 25˚C)
• Input clock amplitude
VCLK 0.2 to 1.0Vp-p (0.4Vp-p Typ.)
• Clock frequency
fCLK
4.433619MHz
• Input clock waveform Sine wave
Block Diagram and Pin Configuration (Top View)
CXL5515M
8 pin SOP (Plastic)
CXL5515P
8 pin DIP (Plastic)
Input Signal Amplitude
VSIG 500mVp-p (Typ.), 575mVp-p (Max.)
Functions
• 848-bit CCD register
• Clock driver
• Auto bias circuit
• Input center bias circuit
• Sample and hold circuit
• Tripling PLL circuit
• Inverted output
Structure
CMOS-CCD
VDD
VCO OUT
VCO IN
8
7
6
CLK
5
Auto-bias circuit
Bias circuit
CCD
(848 bit)
PLL
Timing circuit
Clock driver
Output circuit
(S/H 1 bit)
Bias circuit A
Bias circuit B
1
2
3
4
IN
AB
OUT
VSS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E94904-ST