CXL5512M Datasheet, PDF (1/9 Pages) Sony Corporation – CMOS-CCD 1H Delay Line for NTSC

CXL5512M/P
CMOS-CCD 1H Delay Line for NTSC
Description
The CXL5512M/P are CMOS-CCD delay line ICs
designed for processing video signals. This ICs
provide a 1H delay time for NTSC signals including
the external lowpass filter.
CXL5512M
8 pin SOP (Plastic)
CXL5512P
8 pin DIP (Plastic)
Features
• Single 5 V power supply
• Low power consumption
• Built-in peripheral circuit
• Built-in tripling PLL circuit
• Sync tip clamp mode
Absolute Maximum Ratings (Ta=25 °C)
• Supply voltage
VDD
+6
V
• Operating temperature Topr –10 to +60 °C
• Storage temperature Tstg –55 to +150 °C
• Allowable power dissipation
PD
CXL5512M 350 mW
CXL5512P 480 mW
Recommended Operating Range (Ta=25 ˚C)
VDD 5 V±5 %
Recommended Clock Conditions (Ta=25 ˚C)
• Input clock amplitude VCLK 400mVp-p (Typ.)
• Clock frequency
fCLK 3.579545
MHz
• Input clock waveform Sine wave
Input Signal Amplitude
VSIG 500mVp-p (typ.), 572 mVp-p (max.)
(at internal clamp condition)
Functions
• 680-bit CCD register
• Clock driver
• Auto-bias circuit
• Sync tip clamp circuit
• Sample and hold circuit
• Tripling PLL circuit
• Inverted output
Structure
CMOS-CCD
Block Diagram and Pin Configuration
VDD
VCO OUT
VCO IN
CLK
8
7
6
5
PLL
Auto-bias circuit
Clamp circuit
1
IN
CCD
(680bit)
Output circuit
(S/H 1 bit)
2
3
AB
OUT
Timing circuit
Clock driver
Bias circuit A
Bias circuit B
4
VSS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E93Y19-TE