CXL5506M Datasheet, PDF (1/9 Pages) Sony Corporation – CMOS-CCD 1H Delay Line for PAL

CXL5506M/P
CMOS-CCD 1H Delay Line for PAL
Description
The CXL5506M/P are CMOS-CCD delay line ICs
that provide 1H delay time for PAL signals including
the external low-pass filter.
Features
• Single 5V power supply
• Low power consumption 95mW (Typ.)
• Built-in peripheral circuits
Functions
• 1130-bit CCD register
• Clock driver
• Auto-bias circuit
• Input clamp circuit
• Sample-and-hold circuit
Structure
CMOS-CCD
Blook Diagram and Pin Configuration (Top View)
CXL5506M
8 pin SOP (Plastic)
CXL5506P
8 pin DIP (Plastic)
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VDD
6
V
• Operating temperature Topr –10 to +60 °C
• Storage temperature Tstg –55 to +150 °C
• Allowable power dissipation
PD
CXL5506M 350 mW
CXL5506P 480 mW
Recommended Operating Condition (Ta = 25°C)
Supply voltage
VDD
5 ± 5% V
Recommended Clock Conditions (Ta = 25°C)
• Input clock amplitude VCLK 0.3 to 1.0 Vp-p
(0.5Vp-p typ.)
• Clock frequency
fCLK 17.734475 MHz
• Input clock waveform Sine wave
Input Signal Amplitude
VSIG 575mVp-p (Max.) (at internal clamp condition)
8
7
6
5
Auto-bias circuit
Bias circuit
CCD
(1130bit)
Clamp circuit
1
Output circuit
(S/H 1bit)
2
3
Timing circuit
Clock driver
Bias circuit (A)
Bias circuit (B)
4
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E90632B7X-PS