CXL5505M Datasheet, PDF (1/9 Pages) Sony Corporation – CMOS-CCD 1H Delay Line for PAL

CXL5505M/P
CMOS-CCD 1H Delay Line for PAL
Description
The CXL5505M/P are CMOS-CCD delay line ICs
that provide 1H delay time for PAL signals including
the external low-pass filter.
Features
• Single 5V power supply
• Low power consumption 100mW (Typ.)
• Built-in peripheral circuits
• Built-in quadruple PLL circuit
Functions
• 1130-bit CCD register
• Clock driver
• Auto-bias circuit
• Input clamp circuit
• Sample-and-hold circuit
• PLL circuit
Structure
CMOS-CCD
Blook Diagram and Pin Configuration (Top View)
CXL5505M
14 pin SOP (Plastic)
CXL5505P
14 pin DIP (Plastic)
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VDD
6
V
• Operating temperature Topr –10 to +60 °C
• Storage temperature Tstg –55 to +150 °C
• Allowable power dissipation
PD
CXL5505M 400 mW
CXL5505P 800 mW
Recommended Operating Condition (Ta = 25°C)
Supply voltage
VDD
5 ± 5% V
Recommended Clock Conditions (Ta = 25°C)
• Input clock amplitude VCLK 0.3 to 1.0 Vp-p
(0.5Vp-p typ.)
• Clock frequency
fCLK
4.433619 MHz
• Input clock waveform Sine wave
Input Signal Amplitude
VSIG 575mVp-p (Max.) (at internal clamp condition)
14
13
12
11
10
9
8
Auto-bias circuit
PLL
Clamp circuit
CCD
(1130bit)
Clock driver
Timing circuit
Bias circuit (A)
Output circuit
(S/H 1bit)
Bias circuit (B)
1
2
3
4
5
6
7
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E90731B7X-PS