CXL5502M Datasheet, PDF (1/13 Pages) Sony Corporation – CMOS-CCD 1H Delay Line for NTSC

CXL5502M/N/P
CMOS-CCD 1H Delay Line for NTSC
For the availability of this product, please contact the sales office.
Description
The CXL5502M/N/P are CMOS-CCD delay line ICs
CXL5502M
CXL5502N
that provide 1H delay time for NTSC signals including
14 pin SOP (Plastic) 16 pin SSOP (Plastic)
the external low-pass filter.
The ICs contain a PLL circuit (quadruple progression).
Features
• Single power supply (5V)
• Low power consumption 95mW (Typ.)
• Built-in peripheral circuits
• Clamp level of I/O signal can be selected
• Built-in quadruple PLL circuit
CXL5502P
14 pin DIP (Plastic)
Functions
• 905-bit CCD register
• Clock driver
• Autobias circuit
• Input clamp circuit
• Sample and hold circuit
• PLL circuit (quadruple progression)
Structure
CMOS-CCD
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VDD
6
V
• Operating temperature Topr –10 to +60 °C
• Storage temperature Tstg –55 to +150 °C
• Allowable power dissipation
PD
CXL5502M 400 mW
CXL5502N 260 mW
CXL5502P 800 mW
Recommended Operating Condition (Ta = 25°C)
Supply voltage
VDD
5 ± 5% V
Recommended Clock Conditions (Ta = 25°C)
• Input clock amplitude VCLK 0.3 to 1.0 Vp-p
(0.5Vp-p typ.)
• Clock frequency
fCLK
3.579545 MHz
• Input clock waveform Sine wave
Input Signal Amplitude
VSIG 500mVp-p (Typ.), 572mVp-p (Max.)
(at internal clamp condition)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E89930E79-PS