CXK79M36C162GB Datasheet, PDF (1/25 Pages) Sony Corporation – 18Mb 1x2Lp HSTL High Speed Synchronous SRAMs (512Kb x 36)

SONY ΣRAM^™
CXK79M36C162GB
33/4/5
18Mb 1x2Lp HSTL High Speed Synchronous SRAMs (512Kb x 36)
Preliminary
Description
The CXK79M36C162GB is a high speed CMOS synchronous static RAM with common I/O pins. It is manufactured in com-
pliance with the JEDEC-standard 209 pin BGA package pinout defined for SigmaRAM^™ devices. It integrates input registers,
high speed RAM, output registers, and a two-deep write buffer onto a single monolithic IC. Double Data Rate (DDR) Pipelined
(PL) read operations and Late Write (LW) write operations are supported, providing a high-performance user interface. Positive
and negative output clocks are provided for applications requiring source-synchronous operation.
All address and control input signals are registered on the rising edge of the CK differential input clock.
During read operations, output data is driven valid twice, from both the rising and falling edges of CK, beginning one full cycle
after the address and control signals are registered.
During write operations, input data is registered twice, on both the rising and falling edges of CK, beginning one full cycle after
the address and control signals are registered.
Because two pieces of data are always transferred during read and write operations, the least significant address bit of the in-
ternal memory array is not available as an external address pin to this device. Consequently, the number of external address pins
available to the device is one less than the specified depth of the device (i.e. the 512Kb x 36 device has 18, not 19, external
address pins). And, the user cannot choose the order in which the two pieces of data are read. Read data is always provided in
the same order in which it is written.
Output drivers are series-terminated, and output impedance is programmable via the ZQ control pin. When an external resistor
RQ is connected between ZQ and V_SS, the impedance of the SRAM’s output drivers is set to ~RQ/5.
300 MHz operation (600 Mbps) is obtained from a single 1.8V power supply. JTAG boundary scan interface is provided using
a subset of IEEE standard 1149.1 protocol.
Features
•
3 Speed Bins
-33
-4
-5
Cycle Time / Data Access Time
3.3ns / 1.8ns
4.0ns / 2.1ns
5.0ns / 2.3ns
• Single 1.8V power supply (V_DD): 1.7V (min) to 1.95V (max)
• Dedicated output supply voltage (V_DDQ): 1.4V (min) to V_DD (max)
• HSTL-compatible I/O interface with dedicated input reference voltage (V_REF): V_DDQ/2 typical
• Common I/O
• Double Data Rate (DDR) data transfers
• Pipelined (PL) read operations
• Late Write (LW) write operations
• Burst capability with internally controlled Linear Burst address sequencing
• Burst length of two or four, with automatic address wrap
• Full read/write data coherency
• Differential input clocks (CK and CK)
• Data-referenced output clocks (CQ1, CQ1, CQ2, CQ2)
• Programmable output driver impedance via dedicated control pin (ZQ)
• Depth expansion capability (2 or 4 banks) via programmable chip enables (E2, E3, EP2, EP3)
• JTAG boundary scan (subset of IEEE standard 1149.1)
• 209 pin (11x19), 1mm pitch, 14mm x 22mm Ball Grid Array (BGA) package
18Mb 1x2Lp, HSTL, rev 1.1
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November 8, 2002