CXK77K18R320GB Datasheet, PDF (1/23 Pages) Sony Corporation – 32Mb LW R-R HSTL High Speed Synchronous SRAM (2Mb x 18)

SONY
CXK77K18R320GB
3/33/4
32Mb LW R-R HSTL High Speed Synchronous SRAM (2Mb x 18)
Preliminary
Description
The CXK77K18R320GB is a high speed CMOS synchronous static RAM with common I/O pins, organized as 2,097,152 words
by 18 bits. This synchronous SRAMs integrates input registers, high speed RAM, output registers, and a one-deep write buffer
onto a single monolithic IC. Register - Register (R-R) read operations and Late Write (LW) write operations are supported, pro-
viding a high-performance user interface.
All address and control input signals except G (Output Enable) and ZZ (Sleep Mode) are registered on the rising edge of the K
differential input clock.
During read operations, output data is driven valid from the rising edge of K, one full clock cycle after the address is registered.
During write operations, input data is registered on the rising edge of K, one full clock cycle after the address is registered.
Sleep (power down) capability is provided via the ZZ input signal.
Output drivers are series terminated, and output impedance is programmable via the ZQ input pin. By connecting an external
control resistor RQ between ZQ and V_SS, the impedance of the output drivers can be precisely controlled.
333 MHz operation is obtained from a single 1.8V power supply. JTAG boundary scan interface is provided using a subset of
IEEE standard 1149.1 protocol.
Features
•
3 Speed Bins
-3
-33
-4
Cycle Time / Access Time
3.0ns / 1.6ns
3.3ns / 1.6ns
4.0ns / 2.0ns
• Single 1.8V power supply (V_DD): 1.8V ± 0.1V
Note: 2.5V V_DD is also supported. Please contact Sony Memory Marketing Department for further information.
• Dedicated output supply voltage (V_DDQ): 1.5V to 1.8V typical
• HSTL-compatible I/O interface with dedicated input reference voltage (V_REF): V_DDQ/2 typical
• Register - Register (R-R) read protocol
• Late Write (LW) write protocol
• Full read/write coherency
• Byte Write capability
• Differential input clocks (K/K)
• Asynchronous output enable (G)
• Sleep (power down) mode via dedicated mode pin (ZZ)
• Programmable output driver impedance
• JTAG boundary scan (subset of IEEE standard 1149.1)
• 119 pin (7x17), 1.27mm pitch, 14mm x 22mm Ball Grid Array (BGA) package
32Mb LW R-R, rev 0.8
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December 8, 2004