CXD8302Q Datasheet, PDF (1/10 Pages) Sony Corporation – PLL for CCD Cameras

CXD8302Q
PLL for CCD Cameras
For the availability of this product, please contact the sales office.
Description
The CXD8302Q has the functions needs to
configure a PLL circuit with a timing generator and
external sync signals for a CCD of 480K pixels (EIA,
effective pixels) and 570K pixels (CCIR, effective
pixels).
44 pin QFP (Plastic)
Features
• EIA and CCIR compatible
• Compatible with component digital and composite
digital recording format
• Both SYNC and VD/HD signals can be used for
external sync signals
Applications
CCD cameras
Absolute Maximum Ratings
• Supply voltage
VDD VSS – 0.3 to +7 V
• Input voltage
VI VSS – 0.3 to VDD+0.3 V
• Storage temperature Tstg –40 to +125 °C
Structure
Silicon gate CMOS IC
Recommended Operating Conditions
• Supply voltage
VDD
4.5 to 5.5
V
• Operating temperature Topr
0 to 70
°C
Block Diagram
EXTSYNC 15
EXTHD 14
EXTVD 13
fH
Separation
of fH and fV
fV
65 Clocks
Delay
V reset
19
EXTfH
V latch
MODE1 26
MODE2 31
EIA/CCIR 32
Frequency Division
EIA : 1/572
(1/568)
CCIR: 1/576
(1/567)
2fH
H timing
Frequency Division
EIA : 1/525
CCIR: 1/625
V timing
20 INTfH
41 HD
42 VD
43 SYNC
44 BLK
CLKI 38
8
2 3 4 7 8 9 10 11
INTfH phase setting
37 CLKO
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E94320A52-PP