CXD3204R Datasheet, PDF (1/2 Pages) Sony Corporation – IEEE1394 LSI for D-STB, D-VHS, and DTV

CXD3204R
IEEE1394 LSI for D-STB, D-VHS, and DTV
Description
The CXD3204R is an LSI integrating Link Layer and
Physical Layer conforming to the IEEE1394-1995 serial
bus standard on a single chip.
176-pin LQFP (Plastic)
Link Layer provides MPEG2 transport stream
dedicated input interface and output interface, IEC958
audio stream I/O interface and output interface for D/A
converter as a data interface fo isochronous
communication. Also, a maximum 512 bytes of
asynchronous communication is possible.
Physical Layer provides two poarts for 1394 cable
interface, and supports transfer speed of
Y _{200/100Mbit/s. Also, this layer provides received packet}
data regeneration repeat function, arbitration function
and bus initialization logic.
R ^{This LSI utilizes Apple Computer’s Fire Wire}
technology.
Feature Summary
A _{Ì Conforms to IEEE1394-1995 serial bus standard}
Ì Supports 100Mbps/200Mbps
Ì Link layer
x Supports DVB transport streams
IN ^{x Supports IEC958 audio stream}
x Built-in PID filter function
x 2-channel isochronous simultaneous
transmission/synchronous transmission and
reception
x Supports DMA (2-channel) transfer using host
IM ^bus
x Isochronous data inserted from asynchronous
data port
x Built-in cipher circuit conforming to DTCP format
L x Large capacity FIFO
Â¥ Isochronous Transmit/Receive FIFO:
960 x 32-bit x 2
Â¥ Asynchronous Transmit FIFO: 132 x 33-bit
E _{Â¥ Asynchronous Receive FIFO: 133 x 33-bit}
x CIP header automatic attachment/detection
Ì Physical layer
x Live wire detection function when port is
R _{connected to operation node}
x Automatic shutdown function against stopport for
P^powersaving
x Cable power reduction is detected with cable
power status
x Supports configuration manager cable and power
class definition pin.
x Independent 2-port TpBias
Application
Ì Digital interface for D-STB, D-VHS and DTV
Absolute Max. Ratings (T_A = 25^oC, V_SS = 0V)
Ì Supply voltage
V_DD V_SS-0.5 ~ +4.6
V
Ì Input voltage
V_I V_SS-0.5 ~ V_DD+0.5 V
Ì Output voltage
V_O V_SS-0.5 ~ V_DD+0.5 V
Ì Operating temperature T_OPR -20 ~ +75
o_C
Ì Storage temperature T_STG -55 ~ +150
o_C
Recommended Operating Conditions
Ì Supply voltage
V_DD 3.0 ~ 3.6
V
Ì Operating temperature T_OPR -20 ~ +75
o_C
x Bus initialization and arbitration state machine
logic
x Re-synchronization for reception data for local
clock
x Link-On packet recognition
x DS link encode/decode
x 196.603MHz PLL
Revision 0.0 (5/22/99)
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