37C67X Datasheet, PDF (96/194 Pages) SMSC Corporation – ENHANCED SUPER I/O CONTROLLER WITH FAST IR

Register Definitions
The register definitions are based on the
standard IBM addresses for LPT. All of the
standard printer ports are supported. The
additional registers attach to an upper bit
decode of the standard LPT port definition
to avoid conflict with standard ISA devices. The
port is equivalent to a generic parallel port
interface and may be operated in that mode.
The port registers vary depending on the mode
field in the ecr. The table below lists these
dependencies. Operation of the devices in
modes other that those specified is undefined.
NAME
data
ecpAFifo
dsr
dcr
cFifo
ecpDFifo
tFifo
cnfgA
cnfgB
ecr
Table 40 - ECP Register Definitions
ADDRESS (Note 1)
ECP MODES
+000h R/W
000-001
+000h R/W
011
+001h R/W
All
+002h R/W
All
+400h R/W
010
+400h R/W
011
+400h R/W
110
+400h R
111
+401h R/W
111
+402h R/W
All
FUNCTION
Data Register
ECP FIFO (Address)
Status Register
Control Register
Parallel Port Data FIFO
ECP FIFO (DATA)
Test FIFO
Configuration Register A
Configuration Register B
Extended Control Register
Note 1: These addresses are added to the parallel port base address as selected by configuration
register or jumpers.
Note 2: All addresses are qualified with AEN. Refer to the AEN pin definition.
MODE
Table 41 - Mode Descriptions
DESCRIPTION*
000 SPP mode
001 PS/2 Parallel Port mde
010 Parallel Port Data FIFO mode
011 ECP Parallel Port mode
100 EPP mode (If this option is enabled in the configuration registers)
101 (Reserved)
110 Test mode
111 Configuration mode
*Refer to ECR Register Description
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