LAN91C100FDREVD Datasheet, PDF (79/79 Pages) SMSC Corporation – FEAST FAST ETHERNET CONTROLLER WITH FULL DUPLEX CAPABILITY

FEAST Fast Ethernet Controller with Full Duplex Capability
Chapter 11 LAN91C100FD REV. D Revisions
PAGE(S)
23
SECTION/FIGURE/ENTRY
Bank 0 Offset 0—Transmit
Control Register
CORRECTION
Modified the description of the FDUPLX bit and the
PAD_EN bit
30
Bank 2 Offset C—Interrupt Modified the description of the Interrupt Register bits
Status Register
37
Figure 5.2 - Interrupt
Structure
Modified the interrupt structure figure
41
Typical Flow of Events for Modified the Transmit Flow Routine
Transmit (Auto Release =
0)
77
Figure 10.1 - 208 Pin QFP Modified the package outlines
Package Outline
78
Figure 10.2 - 208 Pin TQFP Modified the package outlines
Package Outlines
65
Removed Application Note Removed: Alliance AS7C256-15, Hyundai HY638256-
LJ15, Winbond 24257AJ-12, Cypress CY7C199-12VC,
Cypress CYC199-15VC
64
Operational Description
Supply Current Active Parameter - Changed Icc Type to
25 ma and Max Icc to 40 ma. Icsby (Standby current)
deleted.
7
Description of Pin
Functions
Pin 175 – Changed to active high signal.
24
Table under Bank 0
Changed RX_OVRN to 0 on High Byte row. Removed
references to RX_OVRN under table.
74
DC Electrical and Timing Updated SRAM Interface Timing information. Added
Section
additional timing parameters.
DATE
REVISED
09/01/02
09/01/02
09/01/02
09/01/02
09/01/02
09/01/02
10/13/00
06/27/00
06/01/00
06/01/00
01/28/00
64
Operational Description
Supply Current Active Parameter - Changed Icc Type to
25 ma and Max Icc to 40 ma. Icsby (Standby current)
deleted.
06/27/00
7
Operational
Pin 175 – Changed to active high signal.
DescriptionDescription of
Pin Functions
06/01/00
23
Table under Bank 0
Changed RX_OVRN to 0 on High Byte row. Removed
references to RX_OVRN under table.
06/01/00
74
DC Electrical and Timing Updated SRAM Interface Timing information. Added 01/28/00
Section
additional timing parameters.
SMSC DS – LAN91C100FD Rev. D
Page 79
PRELIMINARY
Rev. 10/14/2002