COM20051 Datasheet, PDF (7/82 Pages) List of Unclassifed Manufacturers – Integrated Microcontroller and ARCNET (ANSI 878.1) Interface

BASIC ARCHITECTURE
The COM20051 consists of four functional 80C32 ARCHITECTURE AND INSTRUCTION
blocks: the 80C32 microcontroller core, SET
ARCNET network cell (includes 1K of buffer
RAM), programmable address decoder, and The 80C32 microcontroller core is identical to the
programmable interrupt router. The internal 16MHz Intel 80C32 in all respects except for the
architecture of the COM20051 is shown in Figure absence of Timer 2. Please refer to the Intel
1.
Embedded Microcontrollers and Processors
Databook, Volume 1, for details regarding the
The 80C32 microcontroller is a full ROMless 8051 architecture, peripherals, instruction set,
implementation of the popular Intel 8051 series. and programming guide. Note that any access
The ARCNET network core is similar in to the internal ARCNET core or any external
architecture to SMSC's popular COM20020 memorry access is visible on the pins of the
family of ARCNET controllers and retains the COM20051.
same command and status flags of previous
ARCNET controllers. The programmable The following differences apply to the
address decoder maps the ARCNET registers COM20051:
into a 256-byte page anywhere within the
External Data Memory space of the 80C32. The 1. Oscillator frequency is 40MHz instead of
ARCNET core was mapped to the External Data
16MHz. This is necessary to derive a
Memory space to simplify software and
20MHz clock for the ARCNET core. The
application development and for production test
processor still operates at 16MHz.
purposes. ARCNET core is available to the
developer when working with the 8051 emulator. 2. nEA pin - This pin must be tied to ground
When the COM20051 is put into Emulate mode,
for normal internal processor operation.
the internal microcontroller is put into a high
When tied to VCC, the COM20051 will enter
impedance state, thus allowing an external In-
the Emulate mode.
Circuit Emulator (ICE) to program the ARCNET
core. The advantage of this approach versus 3. Unused pins - The COM20051 is packaged
mapping the ARCNET registers into the internal
in a 44-pin PLCC. Network I/O is generated
memory (Special Function) area of the 80C32 is
on the four unused pins of the standard
that dedicated software development tools will
80C32 PLCC package. No DIP package is
not be necessary to debug application software.
available.
Since a majority of 8051 applications use only a
small portion of the Data Memory space, there is 4. Power Down operation - The Power Down
no penalty paid for used address space. There
mode can only be used in conjunction when
will also be no penalty in execution time, since
the internal oscillator is being used. If an
cycle times for external data memory accesses
external oscillator is used and the Power
and internal direct memory moves are identical.
Down mode is invoked, damage may result
The network interrupt can be routed to either of
to the oscillator and to the COM20051.
the two external interrupt ports or can be
assigned to one of the general purpose I/O ports. Clock Speed
The ARCNET interrupt is internally wire ORed
with the external interrupt pin to allow greater The COM20051 processor operates at 16MHz
system flexibility.
and the network controller at a maximum 40MHz
clock rate. A single crystal oscillator is used to
supply the two clocks: a 16MHz processor clock
and a 20MHz network clock for the nominal 2.5
Mbps data rate. Pins 20 and 21 are designated
as crystal inputs. When clocking with an external
7