EMC2106_09 Datasheet, PDF (67/106 Pages) SMSC Corporation – Dual RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Dual RPM-Based Linear Fan Controller with Hardware Thermal Shutdown
Datasheet
Bits 7-6 - PWM_BASE4[1:0] - Determines the base frequency of the PWM4 driver (GPIO3 / PWM4
pin).
Bits 5-4 - PWM_BASE3[1:0] - Determines the base frequency of the PWM3 driver (GPIO2 / PWM3
pin).
Bits 3-2 - PWM_BASE2[1:0] - Determines the base frequency of the PWM2 driver (PWM2 / GPIO4
pin).
Bits 1-0 - PWM_BASE1[1:0] - Determines the base frequency of the PWM1 driver (PWM1).
Table 6.24 PWM_BASEx[1:0] Bit Decode
PWM_BASEX[1:0]
1
0
0
0
0
1
1
0
1
1
BASE FREQUENCY
26.00kHz
19.531kHz
4,882Hz
2,441Hz (default)
6.19 PWM 3 and 4 Divide Registers
Table 6.25 PWM Divide Registers
ADDR R/W REGISTER B7
B6
B5
B4
B3
B2
B1
B0 DEFAULT
2Ch
R/W
PWM 3
Divide
128
64
32
16
8
4
2
1
50h
(80)
2Fh
R/W
PWM 4
Divide
128
64
32
16
8
4
2
1
50h
(80)
The PWM 3 and PWM 4 Divide Registers determine the final frequency of the PWM 3 and PWM 4
drivers respectively. Each driver base frequency is divided by the value of the PWM Divide Register
to determine the final frequency. The duty cycle settings are not affected by these settings, only the
final frequency of the PWM driver. A value of 00h will be decoded as 01h.
6.20 PWM 3 Setting Register
Table 6.26 PWM 3 Setting Register
ADDR R/W REGISTER B7
B6
B5
B4
B3
B2
B1
B0 DEFAULT
2Dh
R/W
PWM 3
Setting
128
64
32
16
8
4
2
1
00h
The PWM 3 Input Register controls the output of the GPIO2 / PWM3 pin when it is configured as a
PWM output. The input code represents the number of counts out of a total of 255 that the output will
be high for.
SMSC EMC2106
67
DATASHEET
Revision 1.78 (04-21-09)