81C17 Datasheet, PDF (6/18 Pages) SMSC Corporation – TWENTY PIN UART (TPUART)

RESETTING THE TPUART
FUNCTIONAL DESCRIPTION
PROGRAMMABLE CONTROL PINS
The TPUART must be reset on power up. Since
there is no external pin allocated for hardware
reset, this is accomplished by writing a One
(HIGH) followed by writing a Zero (LOW) to the
Command Register bit 7. Following reset, the
TPUART enters an idle state in which it can
neither transmit nor receive data.
INITIALIZING THE TPUART
The TPUART is initialized by writing three
control words from the processor. Only a single
address is set aside for Mode, Baud Rate
Select, Interrupt Mask and TX Buffer Registers.
For this to be possible, logic internal to the chip
directs information to its proper destination
based on the sequence in which it was written.
The TPUART provides two programmable
control pins that can be configured to perform
as modem or terminal control handshake
signals. If no handshake signal is required,
these pins can be used as general purpose one
bit Input or Output ports.
nCP1 - is an input only pin that can be
programmed to act as the CTS (Clear To Send)
handshake signal, where it will disable data
transmission by the TPUART after the contents
of the Transmit Shift Register is completely
flushed out. When programmed as 1, nCP1 will
serve as a general purpose 1 bit input port. The
inverted state will be reflected in Status Register
bit 0 (when programmed as CTS or general
purpose input bit).
Following internal reset, the first write to address
zero (i.e. RS = 0) is interpreted as a Mode
Control word. The second write is interpreted as
Interrupt Mask word. The third write is
interpreted as Baud Rate Select. The fourth and
all subsequent writes are interpreted as writes to
the TX Buffer Register.
There is one way in which control logic may
return to anticipating a Mode, Interrupt Mask,
and Baud Rate Select words. This is following
an internal reset. Following initialization, the
TPUART is ready to communicate.
nCP2 - is an Input/Output pin. When configured
as Output, its state is directly controlled by the
host processor via writes to the Control
Register. This will serve the purpose of modem
and terminal handshake signals as RTS (Reset
To Send), and DTR (Data Terminal Ready).
When configured as Input, its inverted state is
reflected in the Status Register bit 1 and read by
the processor. This will serve the purpose of
handshake signals as DCD (Data Carrier
Detect) and DSR (Data Set Ready).
BIT 1
0
0
1
1
MODE REGISTER
BIT 2
0 nCP2 is RTS Output
1 nCP2 is GP Output
X nCP2 is GP Input
X nCP2 is GP Input
6