EMC6D103S Datasheet, PDF (54/84 Pages) SMSC Corporation – Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features

Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features
Datasheet
Note 8.8
These registers are only writable when the associated fan is in manual mode. These
registers become read only when the Lock bit is set. Any further attempts to write to these
registers shall have no effect.
The Current PWM Duty registers store the duty cycle that the chip is currently driving the PWM signals
at. At initial power-on, the duty cycle is 100% and thus, when read, this register will return FFh. After
the Ready/Lock/Start Register Start bit is set, this register and the PWM signals are updated based
on the algorithm described in the Auto Fan Control Operating Mode section and the Ramp Rate
Control logic, unless the associated fan is in manual mode – see below.
Note: When the device is configured for Manual Mode, the Ramp Rate Control logic should be
disabled.
When read, the Current PWM Duty registers return the current PWM duty cycle for the respective
PWM signal.
These registers are read only – a write to these registers has no effect.
Note:
If the current PWM duty cycle registers are written while the part is not in manual mode or
when the start bit is zero, the data will be stored in internal registers that will only be active
and observable when the start bit is set and the fan is configured for manual mode. While the
part is not in manual mode and the start bit is zero, the current PWM duty cycle registers will
read back FFh.
Manual Mode (Test Mode)
In manual mode, when the start bit is set to 1 and the lock bit is 0, the current duty cycle registers are
writable to control the PWMs.
Note: When the lock bit is set to 1, the current duty cycle registers are Read-Only.
The PWM duty cycle is represented as follows:
Table 8.8 PWM Duty vs Register Reading
CURRENT DUTY
0%
VALUE (DECIMAL)
0
VALUE (HEX)
00h
25%
64
40h
50%
128
80h
100%
255
FFh
During spin-up, the PWM duty cycle is reported as 0%.
Notes:
„ The PWMx Current Duty Cycle always reflects the current duty cycle on the associated PWM pin.
„ The PWMx Current Duty Cycle register is implemented as two separate registers: a read-only and
a write-only. When a value is written to this register in manual mode there will be a delay before
the programmed value can be read back by software. The hardware updates the read-only PWMx
Current Duty Cycle register on the beginning of a PWM cycle. If Ramp Rate Control is disabled,
the delay to read back the programmed value will be from 0 seconds to 1/(PWM frequency)
seconds. Typically, the delay will be 1/(2*PWM frequency) seconds.
Revision 0.2 (06-14-06)
54
DATASHEET
SMSC EMC6D103S