LPC47N237 Datasheet, PDF (53/138 Pages) SMSC Corporation – 3.3V I/O CONTROLLER FOR PORT REPLICATORS AND DOCKING STATIONS

3.3v I/O Controller for Port Replicators and Docking Stations
Note 9.3 These registers are available in all modes.
Note 9.4 All FIFOs use one common 16 byte FIFO.
Note 9.5 The ECP Parallel Port Config Reg B reflects the IRQ and DMA channel selected by the Configuration
Registers.
9.6
ECP Implementation Standard
This specification describes the standard interface to the Extended Capabilities Port (ECP). All LPC
devices supporting ECP must meet the requirements contained in this section or the port will not be
supported by Microsoft. For a description of the ECP Protocol, please refer to the IEEE 1284 Extended
Capabilities Port Protocol and ISA Interface Standard, Rev. 1.14, July 14, 1993. This document is available
from Microsoft.
9.6.1 Description
The port is software and hardware compatible with existing parallel ports so that it may be used as a
standard LPT port if ECP is not required. The port is designed to be simple and requires a small number of
gates to implement. It does not do any "protocol" negotiation, rather it provides an automatic high
burst-bandwidth channel that supports DMA for ECP in both the forward and reverse directions.
Small FIFOs are employed in both forward and reverse directions to smooth data flow and improve the
maximum bandwidth requirement. The size of the FIFO is 16 bytes deep. The port supports an automatic
handshake for the standard parallel port to improve compatibility mode transfer speed.
The port also supports run length encoded (RLE) decompression (required) in hardware. Compression is
accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the
next byte is to be repeated. Decompression simply intercepts the RLE byte and repeats the following byte
the specified number of times. Hardware support for compression is optional.
Table 9.3 - ECP Pin Descriptions
NAME
nStrobe
PData 7:0
nAck
PeriphAck (Busy)
PError
(nAckReverse)
Select
TYPE
O
I/O
I
I
I
I
DESCRIPTION
During write operations nStrobe registers data or address into the slave
on the asserting edge (handshakes with Busy).
Contains address or data or RLE data.
Indicates valid data driven by the peripheral when asserted. This signal
handshakes with nAutoFd in reverse.
This signal deasserts to indicate that the peripheral can accept data. This
signal handshakes with nStrobe in the forward direction. In the reverse
direction this signal indicates whether the data lines contain ECP
command information or data. The peripheral uses this signal to flow
control in the forward direction. It is an "interlocked" handshake with
nStrobe. PeriphAck also provides command information in the reverse
direction.
Used to acknowledge a change in the direction the transfer (asserted =
forward). The peripheral drives this signal low to acknowledge
nReverseRequest. It is an "interlocked" handshake with
nReverseRequest. The host relies upon nAckReverse to determine when
it is permitted to drive the data bus.
Indicates printer on line.
SMSC DS – LPC47N237
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DATASHEET
Revision 0.3 (10-26-04)