EMC2105 Datasheet, PDF (53/90 Pages) SMSC Corporation – RPM-Based High Side Fan Controller with Hardware Thermal Shutdown

RPM-Based High Side Fan Controller with Hardware Thermal Shutdown
Datasheet
6.11 Configuration 3 Register
ADDR R/W
22h
R/W
REGISTER
Config 3
Table 6.16 Configuration 3 Register
B7
B6
B5
B4
B3
B2
B1
B0 DEFAULT
-
VIN4_I VIN3 VIN3 VIN2 VIN2 VIN1 VIN1
NV
_EN _INV _EN _INV _EN _INV
00h
The Configuration 3 Register controls the four voltage input channels. This register is software locked.
Bit 6 - VIN4_INV - Determines whether the VIN4 channel data is inverted.
„ ‘0’ (default) - The VIN4 channel data is not inverted.
„ ‘1’ - The VIN4 channel data is inverted. The data presented to the reading registers and compared
against the limits is determined as FFh - the measured input voltage.
APPLICATION NOTE: If the TRIP_SET / VIN4 pin is configured to be used to set the Critical / Thermal Shutdown
temperature associated with the External Diode 1 channel, then this bit cannot be set.
Bit 5 - VIN3_EN - Enables the voltage mode on the External Diode 3 channel.
„ ‘0’ (default) - The External Diode 3 channel operates as a diode channel.
„ ‘1’ - The External Diode 3 channel operates as a voltage input. The DP3 / DN4 / VREF_T3 pin
acts as a reference output voltage and the DN3 / DP4 /. VIN3 pin acts as a voltage input. This
overrides the APD bit in the Configuration 1 Register (20h).
Bit 4 - VIN3_INV - Determines whether the VIN3 channel data is inverted.
Bit 3 - VIN2_EN - Enables the voltage mode on the External Diode 2 channel.
Bit 2 - VIN2_INV - Determines whether the VIN2 channel data is inverted.
Bit 1 - VIN1_EN - Enables the voltage mode on the External Diode 1 channel.
Bit 0 - VIN1_INV - Determines whether the VIN1 channel data is inverted.
APPLICATION NOTE: If the TRIP_SET / VIN4 pin is configured to be used to set the Critical / Thermal Shutdown
temperature associated with the External Diode 1 channel, then neither Bit 1 nor Bit 0 can
be set.
6.12 Interrupt Status Register
ADDR
23h
Table 6.17 Interrupt Status Register
R/W REGISTER B7
Interrupt
R-C
Status
-
Register
B6
B5
B4
B3
B2
B1
B0 DEFAULT
TSD TCRIT GPIO FAN HIGH LOW FAULT
00h
The Interrupt Status Register reports the operating condition of the EMC2105. If any of the bits are set
to a logic ‘1’ (other than TSD and HWS) then the ALERT# pin will be asserted low if the corresponding
channel is enabled. Reading from the status register clears all status bits if the error conditions is
removed. If there are no set status bits, then the ALERT# pin will be released.
The bits that cause the ALERT# pin to be asserted can be masked based on the channel they are
associated with unless stated otherwise.
SMSC EMC2105
53
DATASHEET
Revision 1.72 (11-01-07)