USB4640 Datasheet, PDF (52/64 Pages) SMSC Corporation – High Speed Inter-Chip (HSIC) USB 2.0 Hub and Flash Media Controller

8.6.2.1
High Speed Inter-Chip (HSIC) USB 2.0 Hub and Flash Media Controller
nRESET for EEPROM Configuration
Datasheet
Hardware
reset
asserted
Device
Recovery/
Stabilization
8051 Sets
Configuration
Registers
Attach
USB
Upstream
USB Reset
recovery
Idle
Start
completion
request
response
nRESET
t4
t1
t2
t3
t5
t6
t7
VSS
Figure 8.1 nRESET Timing for EEPROM Mode
Table 8.7 nRESET Timing for EEPROM Mode
NAME
DESCRIPTION
MIN
TYP
t1
nRESET asserted
1
t2
Device recovery/stabilization
t3
8051 programs device configuration
20
t4
USB attach (See Note)
t5
Host acknowledges attach and signals USB reset
100
t6
USB idle
Undefined
t7
Completion time for requests (with or without data
stage)
MAX
500
50
100
5
UNITS
μsec
μsec
msec
msec
msec
msec
msec
8.6.3
Note: All power supplies must have reached the operating levels mandated in Chapter 10, DC
Parameters, prior to (or coincident with) the assertion of nRESET.
USB Bus Reset
In response to the upstream port signaling a reset to the device, the device does the following:
Note: The device does not propagate the upstream USB reset to downstream devices.
1. Sets default address to ‘0’.
2. Sets configuration to: Unconfigured.
3. Negates PRTCTL[3:2] to all downstream ports.
4. Clears all TT buffers.
5. Moves device from suspended to active (if suspended).
6. Complies with Section 11.10 of the USB 2.0 Specification for behavior after completion of the reset
sequence.
The host then configures the device and the device’s downstream port devices in accordance with the
USB 2.0 Specification.
Revision 1.0 (06-09-09)
52
DATASHEET
SMSC USB4640/USB4640i