USB97C201 Datasheet, PDF (43/59 Pages) SMSC Corporation – USB 2.0 ATA/ ATAPI Controller

6.2.1.1 Automatic Retries - Out Transactions
If a packet is received with an incorrect data toggle, the SIE will ACK, but ignores the data packet. If more than 64
bytes received on EP0RX or EP1RX, or if more than 512 bytes are received on EP2, the USB SIE will ignore the
packet and set the appropriate “STALL” bit until the host acknowledges the condition by sending a “CLEAR
FEATURE ENDPOINT STALL” command for that endpoint, or, in the case of Endpoint 0, a SETUP is recieved.
If an error occurs during an OUT transaction, the USB97C201 reloads its USB SIE read pointer back to the
beginning of the buffer. The host then sends another OUT token and retransmits the packet.
Once the packet has been successfully received, the appropriate interrupt bit is set in ISR_0 or ISR_1. The SIE can
handle any number of back-to-back retries, but the host determines how many times a packet is retried.
If an endpoints’s buffer or buffers (in the case of EP2) are full, then the SIE sends a NACK. A TX direction Endpoint
will NAK all OUT packets.
6.2.1.2 Automatic Retries - In Transactions
If an timeout (No response from the host / lost ACK) occurs during an IN transaction, the USB97C201 reloads its
USB SIE side buffer read pointer back to the beginning of the failed packet. The host then sends another IN token
and the SIE re-transmits the packet with the same data toggle PID.
Once the host has successfully received the packet (only upon ACK received by SIE), the appropriate interrupt bit is
set in ISR_0 or ISR_1. The SIE can handle any number of back-to-back retries, but the host determines how many
times a packet is retried.
Upon reception of a SETUP token followed by the 8 byte DATA-0 packet on EP0, the internal DTOG bit for both
EP0RX and EP0TX are set to one.
6.2.1.3 Packet Lengths
The maximum packet length of an endpoint is fixed and 64 bytes for EP0 and EP1, and is 512 bytes for EP2 in HS
mode and 64 bytes in FS mode. For IN transactions, the USB97C201 will send the bytes in the buffer to the host.
For all OUT packets, the number of bytes received in the packet is indicated to the 8051 through the BYTE COUNT
Register of the respective endpoint.
6.2.2 USB EVENTS
There are several events, which cause different parts of the SIE to be initialized. The following is the list of events
and the respective actions.
6.2.2.1 Reset
A reset via the external nRESET pin causes the following:
1. All endpoints are disabled, all SIE endpoint buffers are cleared, all stall conditions, and all registers clear to their
default state.
2. If USB97C201 was in power down state, then it is cleared.
3. The external crystal oscillator is allowed to run.
6.2.2.2 USB Bus Reset
USB Bus Reset is recognized only when the clocks are running. If the device is in SUSPEND mode with the clocks
stopped, a USB RESET will be first recognized as a RESUME event and if the WU_SRC1 bit for RESUME is
unmasked, will restart the clocks. The USB RESET can only then be detected. Upon recognition it causes the
following:
1. All SIE endpoint buffer byte count registers are cleared, all stall conditions, the SETUP bit, SETUP_DELAY bit,
SIE_SUSPEND, SIE_RESUME are cleared. The PID sequencers, internal DTOG are reset for all endpoints
2. The following registers will be set to their POR values: USB_ADD, SIE_STAT, USB_CONF, EP0RX_CTL,
EP0TX_CTL, EP1RX_CTL, EXP1TX_CTL, EP2_CTL, EP0RX_BC, EP0TX_BC, EP1RX_BC, EP1TX_BC,
RAMWRBC_A1, RAMWRBC_A2, RAMWRBC_B1, RAMWRBC_B2, RAMRDBC_A1, RAMRDBC_A2,
RAMRDBC_B1, RAMRDBC_B2, NAK, USB_ERR.
3. The seven bit USB device address is cleared.
4. Both EP0TX and EP0RX endpoints are enabled.
5. If the USB_RESET and USB_STAT bits are unmasked, then a ISR_0 interrupt (USB_STAT) is generated to the
8051 and the USB_RESET bit in the WU_SRC1 register will also be set and will generate an interrupt if
unmasked.
SMSC DS – USB97C201
Page 43
PRELIMINARY
Rev. 03/25/2002