EMC1188 Datasheet, PDF (41/48 Pages) Microchip Technology – Notebook Computers

Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications
Datasheet
Table 6.20 Substrate Diode Ideality Factor Look-Up Table (BJT Model) (continued)
SETTING
FACTOR
SETTING
FACTOR
SETTING
FACTOR
16h
1.0053
17h
1.0066
26h
1.0265
27h
1.0278
36h
1.0473
37h
1.0486
APPLICATION NOTE: When measuring a 65nm Intel CPU, the Ideality Setting should be the default 12h. When
measuring a 45nm Intel CPU, the Ideality Setting should be 15h.
6.16 High Limit Status Register 35h
Table 6.21 High Limit Status Register
ADDR. R/W REGISTER B7
B6
B5
B4
B3
B2
B1
B0 DEFAULT
35h
R-C
High Limit
Status
-
-
-
- E3HIGH E2HIGH EHIGH IHIGH
00h
6.17
The High Limit Status Register contains the status bits that are set when a temperature channel high
limit is exceeded. If any of these bits are set, the HIGH status bit in the Status Register is set. Reading
from the High Limit Status Register will clear all bits if. Reading from the register will also clear the
HIGH status bit in the Status Register.
The ALERT pin will be set if the programmed number of consecutive alert counts have been met and
any of these status bits are set.
The status bits will remain set until read unless the ALERT pin is configured as a comparator output
(see Section 5.5.2).
Bit 3 - E3HIGH - This bit is set when the External Diode 3 channel exceeds its programmed high limit.
Bit 2 - E2HIGH - This bit is set when the External Diode 2 channel exceeds its programmed high limit.
Bit 1 - E1HIGH - This bit is set when the External Diode 1 channel exceeds its programmed high limit.
Bit 0 - IHIGH - This bit is set when the Internal Diode channel exceeds its programmed high limit.
Low Limit Status Register 36h
ADDR.
R/W
36h
R-C
REGISTER
Low Limit
Status
Table 6.22 Low Limit Status Register
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
-
-
-
- E3LOW E2LOW ELOW ILOW
00h
The Low Limit Status Register contains the status bits that are set when a temperature channel drops
below the low limit. If any of these bits are set, then the LOW status bit in the Status Register is set.
Reading from the Low Limit Status Register will clear all bits. Reading from the register will also clear
the LOW status bit in the Status Register.
The ALERT pin will be set if the programmed number of consecutive alert counts have been met and
any of these status bits are set.
SMSC EMC1188
41
DATASHEET
Revision 1.0 (07-11-13)