EMC2104_11 Datasheet, PDF (37/99 Pages) SMSC Corporation – Dual RPM-Based PWM Fan Controller with Hardware Thermal Shutdown

Dual RPM-Based PWM Fan Controller with Hardware Thermal Shutdown
Datasheet
Diode 2
Diode 1
Local Ground
Typical remote
substrate transistor
i.e. CPU substrate PNP
to
to
to
DP
DP
DP
to
DN
to
to
DN
DN
Typical remote
discrete PNP transistor
i.e. 2N3906
Typical remote
discrete NPN transistor
i.e. 2N3904
Anti-parallel diodes using
discrete NPN transistors
Figure 5.7 Diode Connections
5.13.1
Diode Faults
The EMC2104 actively detects an open and short condition on each measurement channel. When a
diode fault is detected, the temperature data MSByte is forced to a value of 80h and the FAULT bit is
set in the Status Register. When the External Diode 3 channel is configured to operate in APD mode,
the circuitry will detect independent open fault conditions, however a short condition will be shared
between the External Diode 3 and External Diode 4 channels.
5.14
GPIOs
The EMC2104 contains up to three (3) GPIOs pin (all are multiplexed with other functions). The GPIO
pins can be configured as an input or an output and as a push-pull or open-drain output. Additionally,
the GPIO pins, when configured as an input, can be enabled to trigger an interrupt when they change
states.
5.15
Interrupts
If a change of state occurs (such as a temperature out-of-limit condition or a GPIO changing states)
then the following will occur:
1. The appropriate status bits will be set in the Status Register and in the High, Low, and Fault Status
Registers.
2. The ALERT# will be asserted if the specific channel interrupt is enabled (see Section 6.15).
The ALERT# pin is cleared by setting the MASK bit, disabling the specific interrupt channel enable, or
reading the status registers. If the error conditions persist, then the status bits will remain set. Unless
the Interrupt Status Enable bits are cleared or the MASK bit is set, the ALERT# pin will likewise be set.
SMSC EMC2104
37
DATASHEET
Revision 1.78 (02-28-11)