EMC6D102_06 Datasheet, PDF (36/86 Pages) SMSC Corporation – Fan Control Device with Hardware Monitoring and Acoustic Noise Reduction Features

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Fan Control Device with Hardware Monitoring and Acoustic Noise Reduction Features
Datasheet
Table 6.1 PWM Ramp Rate (continued)
PWM RAMP TIME (SEC)
(TIME FROM 33%
DUTY CYCLE TO
100% DUTY CYCLE)
1.6
0.8
PWM RAMP TIME (SEC)
(TIME FROM 0% DUTY
CYCLE TO 100% DUTY
CYCLE)
2.55
1.275
TIME PER
PWM STEP
(PWM STEP SIZE =
1/255)
10 msec
5 msec
PWM
RAMP
RATE
(HZ)
100
200
Example 1: PWM period < Ramp Rate Step Size
PWM frequency = 87.7Hz (11.4msec) & PWM Ramp Rate = 38.46Hz (26msec)
Calculate Duty Cycle
Ramping Duty Cycle
PWM Duty Cycle
70h
70h
70h
74h
71h
72h
73h
74h
26ms
26ms
26ms
26ms
71h ^71h 71h ^72h 72h 73h ^{73h 73h} 74h ^74h 74h
11.4ms 11.4ms 11.4ms 11.4ms 11.4ms 11.4ms 11.4ms 11.4ms 11.4ms 11.4ms
Example 2: PWM period > Ramp Rate Step Size
PWM frequency = 11Hz (90.9msec) & PWM Ramp Rate = 38.46Hz (26msec)
Calculate Duty Cycle
70h
74h
Ramping Duty Cycle
70h
71h
26ms
PWM Duty Cycle
70h
72h
26ms
71h
90.9msec
73h
26ms
74h
26ms
74h
Figure 6.4 Illustration of PWM Ramp Rate Control
Notes:
„ The PWM Duty Cycle latches the Ramping Duty Cycle on the rising edge of the PWM output.
„ The calculated duty cycle, ramping duty cycle, and the PWM output duty cycle are asynchronous
to each other, but are all synchronized to the internal 90kHz clock source.
It should be noted that the actual duty cycle on the pin is created by the PWM Ramp Rate Control
block and latched on the rising edge of the PWM output. Therefore, the current PWM duty cycle may
lag the PWM Calculated Duty Cycle.
Revision 0.4 (06-15-06)
36
DATASHEET
SMSC EMC6D102