LAN9220 Datasheet, PDF (33/150 Pages) SMSC Corporation – 16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support

16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support
Datasheet
FIELD
31:28
27:16
15:12
11:0
Table 3.7 TX Checksum Preamble
DESCRIPTION
RESERVED
TXCSLOC - TX Checksum Location
This field specifies the byte offset where the TX checksum will be inserted in the TX packet. The
checksum will replace two bytes of data starting at this offset.
Note: The TX checksum cannot be inserted in the MAC header (first 14 bytes) or in the last 4
bytes of the TX packet.
RESERVED
TXCSSP - TX Checksum Start Pointer
This field indicates start offset, in bytes, where the checksum calculation will begin in the associated
TX packet.
Note: The data checksum calculation must not begin in the MAC header (first 14 bytes) or in
the last 4 bytes of the TX packet.
Note: When the TXCOE is enabled, the third DWORD of the pre-pended packet is not transmitted.
However, 4 bytes must be added to the packet length field in TX Command ‘B’.
Note: The TX checksum preamble must be DWORD-aligned (i.e., the two least significant bits of the
Data Start Offset fields in TX Command “A” must be zero). Any valid buffer end alignment
setting can be used.
Note: Software applications must stop the transmitter and flush the TX data path before changing the
state of the TXCOE_EN bit. However, the CK bit of TX Command ‘B’ can be set or cleared on
a per-packet basis.
3.6.2.1
3.7
3.7.1
3.7.2
TX Checksum Calculation
The TX checksum calculation is performed using the same operation as the RX checksum shown in
Section 3.6.1.1, with the exception that the calculation starts as indicated by the preamble, and the
transmitted checksum is the one’s-compliment of the final calculation.
Host Bus Operations
Bus Writes
The host processor is required to perform two contiguous 16-bit writes to complete a single DWORD
transfer. This DWORD must begin and end on a DWORD address boundary (A[2] and higher, cannot
change during a sixteen bit write). No ordering requirements exist. The processor can access either
the low or high word first, as long as the next write is performed to the other word. If a write to the
same word is performed, the LAN9220 disregards the transfer.
Bus Reads
The host processor is required to perform two consecutive 16-bit reads to complete a single DWORD
transfer. This DWORD must begin and end on a DWORD address boundary (A[2] and higher, cannot
change during a sixteen bit read). No ordering requirements exist. The processor can access either
the low or high word first, as long as the next read is performed from the other word. If a read to the
same word is performed, the data read is invalid and should be re-read. This is not a fatal error. The
LAN9220 will reset its read counters and restart a new cycle on the next read.
SMSC LAN9220
33
DATASHEET
Revision 2.6 (12-04-08)