CIRCC Datasheet, PDF (28/70 Pages) SMSC Corporation – Consumer Infrared Communications Controller

Line Control Register B (Address 5)
SCE Modes, bits 6 - 7
The SCE Modes bits enable the SCE transmitter
and receiver (Table 16). These bits are R/W and
must be manually reset by the host following CIR
message transactions when the FRAME bit is
one. The SCE Modes bits are automatically
reset by the hardware following FIFO Overruns
or Underruns. Note: The SCE Modes bits must
be zero for loopback tests.
Table 16 - SCE Modes
D7 D6
MODE DESCRIPTION
0 0 Receive/Transmit Disabled (default)
0 1 Transmit Mode
1 0 Receive Mode
1 1 Undefined
Transmit Mode
Transmit mode enables the SCE Consumer IR
transmitter whenever TC goes active, or the
FIFO THRESHOLD has been exceeded (see the
Transmit Timing section on page 54). In
Transmit mode, the SCE FIFO input is
connected to the Host System Data Bus and the
FIFO output is connected to the SCE transmitter
input. The Consumer IR encoder will reset
Transmit mode in hardware following the rising
edge of nActive Frame following a FIFO
underrun.
Receive Mode
Receive mode enables the SCE Consumer IR
receiver (see the Receive Timing section on
page 54). In Receive mode, the SCE FIFO
output is connected to the Host System Data
Bus, the FIFO input is connected to the SCE
receiver output. The Consumer IR encoder will
reset Receive mode in hardware following the
rising edge of nActive Frame following a FIFO
underrun or TC.
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