LPC47B37X Datasheet, PDF (233/254 Pages) SMSC Corporation – 100 Pin Enhanced Super I/O for LPC Bus with SMBus Controller for Commercial Applications

t1
t2
nWRITE
PD<7:0>
t3
t4
t5
t6
t7
t8
t9
t10
nDATASTB
nADDRSTB
nWAIT
t11
t12
FIGURE 18 – EPP 1.9 DATA OR ADDRESS READ CYCLE
NAME
DESCRIPTION
MIN TYP MAX
t1 nWAIT Asserted to nWRITE Deasserted
0
185
t2 nWAIT Asserted to nWRITE Modified (Notes 1,2)
60
190
t3 nWAIT Asserted to PDATA Hi-Z (Note 1)
60
180
t4 Command Asserted to PDATA Valid
0
t5 Command Deasserted to PDATA Hi-Z
0
t6 nWAIT Asserted to PDATA Driven (Note 1)
60
190
t7 PDATA Hi-Z to Command Asserted
0
30
t8 nWRITE Deasserted to Command
1
t9 nWAIT Asserted to Command Asserted
0
195
t10 nWAIT Deasserted to Command Deasserted
60
180
(Note 1)
t11 PDATA Valid to nWAIT Deasserted
0
t12 PDATA Hi-Z to nWAIT Asserted
0
Note 1: nWAIT is considered to have settled after it does not transition for a minimum of 50 ns.
Note 2: When not executing a write cycle, EPP nWRITE is inactive high.
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
233