37B77X Datasheet, PDF (187/196 Pages) SMSC Corporation – ENHANCED SUPER I/O CONTROLLER WITH WAKE UP FEATURES

Output Drivers
To facilitate higher performance data transfer,
the use of balanced CMOS active drivers for
critical signals (Data, HostAck, HostClk,
PeriphAck, PeriphClk) are used ECP Mode.
Because the use of active drivers can present
compatibility problems in Compatible
Mode (the control signals, by tradition, are
specified as open-collector), the drivers are
dynamically changed from open-collector to
totem-pole. The timing for the dynamic driver
change is specified in then IEEE 1284
Extended Capabilities Port Protocol and ISA
Interface Standard, Rev. 1.14, July 14, 1993,
available from Microsoft. The dynamic driver
change must be implemented properly to
prevent glitching the outputs.
PDATA
t6
t3
nSTROBE
t1
t2
t5
t4
BUSY
FIGURE 16 - PARALLEL PORT FIFO TIMING
NAME
DESCRIPTION
MIN TYP MAX UNITS
t1 DATA Valid to nSTROBE Active
600
ns
t2 nSTROBE Active Pulse Width
600
ns
t3 DATA Hold from nSTROBE Inactive (Note 1)
450
ns
t4 nSTROBE Active to BUSY Active
500
ns
t5 BUSY Inactive to nSTROBE Active
680
ns
t6 BUSY Inactive to PDATA Invalid (Note 1)
80
ns
Note 1: The data is held until BUSY goes inactive or for time t3, whichever is longer. This only
applies if another data transfer is pending. If no other data transfer is pending, the data is
held indefinitely.
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