USB2227 Datasheet, PDF(18/26 Page) SMSC Corporation – 4TH GENERATION USB2.0 FLASH MEDIA CONTROLLER WITH INTEGRATED CARD POWER FETS

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USB2227 Datasheet, PDF (18/26 Pages) SMSC Corporation – 4TH GENERATION USB2.0 FLASH MEDIA CONTROLLER WITH INTEGRATED CARD POWER FETS

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NAME

Memory Address

Bus

Memory Write

Strobe

Memory Read

Strobe

Memory Chip

Enable

General Purpose

I/O

General Purpose

I/O

General Purpose

I/O

General Purpose

I/O

General Purpose

I/O

SYMBOL

MA[1:0]/CLK_S

EL[1:0]

nMWR

nMRD

nMCE

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

4th Generation USB2.0 Flash Media Controller with Integrated Card Power FETs

Datasheet

BUFFER

TYPE

I/O8PD

DESCRIPTION

MA[1:0], These signals address memory locations

within the external memory.

SEL[1:0]. During nRESET assertion, these pins will

select the operating frequency of the external clock, and

the corresponding weak pull-down resistors are

enabled. When nRESET is negated, the value on these

pins will be internal latched and these pins will revert to

MA[1:0] functionality, the internal pull-downs will be

disabled.

SEL[1:0] = â00â. 24MHz

SEL[1:0] = â01â. RESERVED

SEL[1:0] = â10â. RESERVED

SEL[1:0] = â11â. 48MHz

Note:

If the latched value is â1â, then the

corresponding MA pin is tri-stated when the

following conditions are true:

1. IDLE bit (PCON.0) is 1.

2. INT2 is negated

3. SLEEP bit of CLOCK_SEL is 1.

If the latched value is â0â, then the corresponding MA pin

will function identically to the MA[15:3] pins at all times

(other than during nRESET assertion).

Program Memory Write; active low

Program Memory Read; active low

Program Memory Chip Enable; active low.

This signal is asserted, when any of the following

conditions are no longer met:

1. IDLE bit (PCON.0) is 1.

2. INT2 is negated

3. SLEEP bit of CLOCK_SEL is 1.

Note: This signal is held to a logic âhighâ while

nRESET is asserted.

MISC

I/O8