FDC37C93X Datasheet, PDF (179/203 Pages) SMSC Corporation – Plug and Play Compatible Ultra I/O Controller

t1
t2
t2
X1K
FIGURE 7A - INPUT CLOCK TIMING
NAME
DESCRIPTION
t1 Clock Cycle Time for 14.318MHZ
t2 Clock High Time/Low Time for 14.318MHz
t1 Clock Cycle Time for 32KHZ
t2 Clock High Time/Low Time for 32KHz
Clock Rise Time/Fall Time (not shown)
MIN TYP MAX UNITS
65
ns
25
ns
5
ns
t4
RESET
FIGURE 7B - RESET TIMING
NAME
DESCRIPTION
t4 nRESET Low Time (Note 1)
MIN TYP MAX UNITS
1.5
µs
Note 1: The nRESET low time is dependent upon the processor clock. The nRESET must be active
for a minimum of 24 x16MHz clock cycles.
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